HSP50110 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Lista de partido

HSP50110

Digital Quadrature Tuner

Intersil 

Pinout

HSP50110

HSP50110 (PLCC)

TOP VIEW

IIN5

IIN4

IIN3

IIN2

GND

IIN1

IIN0

ENI

QIN9

QIN8

QIN7

QIN6

QIN5

QIN4

VCC

QIN3

QIN2

QIN1

QIN0

PH1

PH0

11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

12

74

13

73

14

72

15

71

16

70

17

69

18

68

19

67

20

66

21

65

22

64

23

63

24

62

25

61

26

60

27

59

28

58

29

57

30

56

31

55

32

54

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

IOUT3

IOUT2

IOUT1

IOUT0

DATARDY

VCC

CLK

GND

QOUT9

QOUT8

QOUT7

QOUT6

QOUT5

GND

QOUT4

QOUT3

QOUT2

QOUT1

QOUT0

OEQ

VCC

Pin Descriptions

NAME

VCC

GND

IIN9-0

QIN9-0

ENI

PH1-0

CFLD

COF

COFSYNC

TYPE

DESCRIPTION

- +5V Power Supply.

- Ground.

I In-Phase Input. Data input for in-phase (real) samples. Format may be either two’s complement or offset binary format

(see I/O Formatting/Control Register in Table 9). IIN9 is the MSB.

I Quadrature Input. Data input for quadrature (imaginary) samples. Format may be either two’s complement or offset bi-

nary format (see I/O Formatting/Control Register in Table 9). QIN9 is the MSB.

I Input Enable. When ENI is active ‘low’, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the rising

edge of CLK. This input also controls the internal data processing as described in the Input Controller Section of the

data sheet. ENI is active ‘low’.

I Carrier Phase Offset. The phase of the internally generated carrier frequency may be shifted by 0, 90, 180, or 270 de-

grees by controlling these pins (see Synthesizer/Mixer Section). The phase mapping for these inputs is given in Table 1.

I Carrier Frequency Load. This input loads the Carrier Frequency Register in the Synthesizer NCO (see

Synthesizer/Mixer Section). When this input is sampled ‘high’ by clock, the contents of the Microprocessor Interface

Holding Registers are transferred to the carrier frequency register in the Synthesizer NCO (see Microprocessor Inter-

face Section). NOTE: This pin must be ‘low’ when loading other configuration data via the Microprocessor In-

terface. Active high Input.

I Carrier Offset Frequency Input. This serial input is used to load the Carrier Offset Frequency into the Synthesizer NCO

(see Serial Interface Section). The new offset frequency is shifted in MSB first by CLK starting with the clock cycle after

the assertion of COFSYNC.

I Carrier Offset Frequency Sync. This signal is asserted one CLK cycle before the MSB of the offset frequency data word

(see Serial Interface Section).

2

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