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HSP50110

Digital Quadrature Tuner

Intersil 

HSP50110

of the accumulator output is shown in Figure 3. The AGC

gain is given by:

GainAGC = (1.0 + M) x 2E

(EQ. 7)

MAPS TO AGC

UPPER AND LOWER LIMITS

LLLLLLLL

22 21 20. 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-102-112-122-13

E E E M M M M X GG G G G G G G

MANTISSA

0.0 to 0.9375

PROGRAMMABLE

LOOP GAIN

EXPONENT

0 TO 7

MAPS TO µP AGC

LOOP FILTER ACCUMULATOR PARAMETER

This Value Can Be Read By The Microprocessor.

See The Microprocessor Interface Section.

FIGURE 3. BINARY FORMAT FOR LOOP FILTER

ACCUMULATOR

where M is the 4-bit mantissa value ranging from 0.0 to

0.9375, and E is the three bit exponent ranging from 0 to 7.

The result is a piece wise linear transfer function whose

overall response is logarithmic, as shown in Figure 5. The

exponent bits provide a coarse gain setting of 2(EEE). This

corresponds to a gain range from 0dB to 42dB (20 to 27) with

the MSB representing a 24dB gain, the next bit a 12dB gain,

and the final bit a 6dB gain. The four mantissa bits map to an

additional gain of 1.0 to 1.9375 (0 to ~6dB). Together, the

exponent and the mantissa portion of the limit set a gain

range from 0 to ~48dB.

AGC L.D. SENSE †

AGC THRESHOLD †

AGC LOOP FILTER

AGC

DISABLE †

REG

LIMIT +

REG

LEVEL

DETECTOR

UPPER

GAIN

LIMIT †

LOWER

GAIN

LIMIT †

Q DATA

I DATA

PROGRAMMABLE

LOOP GAIN †

† Indicates data downloaded via microprocessor interface.

FIGURE 4. AGC BLOCK DIAGRAM

The limiter restricts the AGC gain range by keeping the

accumulator output between the programmed limits. If the

accumulator exceeds the upper or lower limit, then the

accumulator is held to that limit. The limits are programmed

via eight bit words which express the values of the upper and

lower limits as eight bit pseudo floating point numbers as

shown in Figure 3 (see AGC Control Register, Table 8). The

format for the limits is the same as the format of the eight

most significant bits of the Loop Filter Accumulator.

Examples of how to set the limits for a specific output signal

level are provided in the “Setting DQT Gains” Section below.

NOTE: A fixed AGC gain may be set by programming

the upper and lower limits to the same value.

256

48

240

224

42

208

192

36

176

160

dB

30

144

128

24

112

LINEAR

96

18

80

64

12

48

32

6

16

0

0

0 16 32 48 64 80 96 112128 144 160 176192 208 224 240

GAIN CONTROL WORD

(8 MSBs OF LOOP FILTER ACCUMULATOR)

FIGURE 5. GAIN CONTROL TRANSFER FUNCTION

The response time of the AGC is determined by the

Programmable Loop Gain. The Loop Gain is an unsigned

8-bit value whose significance relative to the AGC gain is

shown in Figure 3. The loop gain is added or subtracted from

the accumulator depending on the output of the Level

Detector. The accumulator is updated at the output sample

rate. If the accumulator exceeds the upper or lower limit, the

accumulator is loaded with that limit. The slew rate of the

AGC ranges between ~0.001dB and 0.266dB per output

sample for Loop Gains between 01(HEX) and FF (HEX)

respectively.

The user should exercise care when using maximum loop

gain when the (x/sin(x)) or the (x/sin(x))3 compensation filter is

enabled. At high decimation rates, the delay through the

compensation filter may be large enough to induce

oscillations in the AGC loop. The Basic Architectural

Configurations Section contains the necessary detailed block

diagrams to determine the loop delay for different matched

filter configurations.

Low Pass Filtering

The gain corrected signal feeds a Low Pass Filtering Section

comprised of a Cascaded Integrator Comb (CIC) and

compensation filter. The filtering section extracts the channel

of interest while providing decimation to match the output

sample rate to the channel bandwidth. A variety of filtering

configurations are possible which include integrate and

dump, integrate and dump with x/sin(x) compensation, third

order CIC, and third order CIC with ((x)/sin(x))3

compensation. If none of these filtering options are desired,

the entire filtering section may be bypassed.

7

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