XR16C850 Ver la hoja de datos (PDF) - Exar Corporation

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XR16C850

UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control

Exar Corporation 

XR16C850

SYMBOL DESCRIPTION

Symbol

40

IRQB/-RXRDY 29

IRQC/-TXRDY 24

-LPT-1 /

-BAUDOUT

15

-LPT2/-DDIS

23

Pin

44 48

32 29

27 23

17 12

26 22

Signal

52 type

Pin Description

MCR bit-3 is set to a logic 1, interrupts are enabled

in the interrupt enable register (IER), and when an

interrupt condition exists. Interrupt conditions in-

clude: receiver errors, available receiver buffer data,

transmit buffer empty, or when a modem status flag

is detected. During STD mode operation the three

state mode is disabled and this pin functions as INT

(Interrupt Request).

32

O Interrupt Request “B” or Receive Ready (three state,

dual function) -. During PC mode operation, a logic

1 indicates an interrupt IRQB (see further descrip-

tion under the IRQA). During the STD mode a logic

0 indicates receive data ready status, i.e. the RHR

is full or the FIFO has one or more RX characters

available for unloading. This pin goes to a logic 0

when the FIFO/RHR is full or when there are more

characters available in either the FIFO or RHR.

25

O Interrupt Request “C” or Transmit Ready (three

state, dual function) - During PC mode operation, a

logic 1 on this pin indicates an interrupt IRQC (see

further description under the IRQA). During the STD

mode buffer ready status is indicated by a logic 0,

i.e., at least one location is empty and available in

the FIFO or THR. This pin goes to a logic 1 when

there are no more empty locations in the FIFO or

THR.

12

O Baud Rate Generator Output or Line Printer Port-1

Decode Logic Output. (dual function, active low) -

When the PC mode is selected, the baud rate

generator clock output is internally connected to the

RCLK input. This pin then functions as the LPT-1

printer port decode logic output, see table 2. During

STD mode operation, this pin provides the 16X clock

of the selected data rate from the baud rate genera-

tor. The RCLK pin must be connected externally to

-BAUDOUT when the receiver is operating at the

same data rate.

24

O Drive Disable or Line Printer Port-2 Decode Logic

Output (dual function, active low) - When the PC

Rev. 1.20

8

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