Z9975 Ver la hoja de datos (PDF) - Cypress Semiconductor
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Z9975 Datasheet PDF : 8 Pages
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Z9975
Maximum Ratings¹
Input Voltage Relative to VSS:
Input Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
VSS-0.3V
VDD+0.3V
-65°C to + 150°C
-40°C to +85°C
5.5V
3.3V, 150MHz, Multi-Output Zero Delay Buffer
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Input Pin Capacitance
Symbol Min
Typ Max Units Conditions
VIL
VSS
-
0.8
Vdc
VIH
2.0
- VDD Vdc
Applicable to all input signals.
IIL
-100 µA
IIH
100
µA
VOL
0.5
V
IOL = 20 mA
VOH
2.4
V
IOH = - 20mA
Idd
-
-
20
mA
Cin
-
-
8
pF
Per input
VDD* =3.3V + 5%, TA = -40°C to +85°C
PLL AC Parameters
Characteristic
Symbol
Min
Typ
Max Units Conditions
Maximum PLL Lock Time
tLOCK
10
mS Stable power supply & valid clocks
presented on TCLK(0:1) pins.
VCO Lock Range
fVCO
200
500 MHz
FselFB(0:1) = /4 to /12
TCLK(0:1) input rise / fall
time
Tinr, Tinf
3
nS
Input Reference frequency
fREF
Note 2
Note 2 MHz
Input Reference duty cycle fREFpw
25
75
%
VDD* = 3.3V + 5%, TA = -40°C to +85°C
Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is
NOT required.
Note 2: Input Reference Frequency is limited by the divider selection and the VCO lock range.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
Page 5 of 8
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