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RTL8196

IEEE 802.11n AP/ROUTER NETWORK PROCESSOR WITH EEE

Realtek Semiconductor 

RTL8196C

Datasheet

6.4.2. DRAM Configuration Register (DCR) (0xB800_1004)

This register does not provide byte access.

Table 5. DRAM Configuration Register (DCR) (0xB800_1004)

Bit Name

Description

Mode Default

31:30 T_CAS

CAS Latency

RW 01B

00: Latency=2

01: Latency=3

10: Latency=2.5

11: Reserved

29:28 DBUSWID

DRAM Bus Width

RW 01B

00: Reserved

01: 16-bit

10: Reserved

11: Reserved

27 DCHIPSEL

26:25 ROWCNT

24:22 COLCNT

ltekL 21 BSTREF

a IA 20 ARBIT

T 19 BANKCNT

Re EN ION 18 FAST_RX

ID RAT 17 MR_MODE

NF RPO 16 DRV_STR

CforOZTE CO 15:0 Reserved

DRAM Chip Select

RW

0: Test mode

1: Normal mode

Row Counts

RW

00: 2K (A0~A10)

01: 4K (A0~A11)

10: 8K (A0~A12)

11: 16K (A0~A13)

Column Counts

RW

000: 256 (A0~A7)

001: 512 (A0~A8)

010: 1K (A0~A9)

011: 2K (A0~A9, A11)

100: 4K (A0~A9, A11, A12) 101: Reserved

110: Reserved

111: Reserved

Bursted 8 Auto-Refresh Commands (Used for DDR)

RW

0: Disable

1: Enable

Enforce Interface Arbitration to Take Effect

RW

0: Reserved

1: Take effect

Bank Counts

RW

0: 2 banks (used for SDR)

1: 4 banks (used for SDR, DDR)

If RX path turnaround delay is small enough, the memory controller

RW

can return read data with reduced latency within 1DRAM clock cycle

(used for DDR).

0: Normal path

1: Fast path

Select the Memory Command that the Memory Controller Issues (Used RW

for DDR)

0: Mode Register

1: Extended Mode Register

Drive Strength Setting of DRAM Chip (Used for DDR)

RW

For this option to be effective, MR_MODE must be first set to 1.

0: Normal

1: Reduced

Reserved

-

1B

00B

000B

0B

0B

1B

0B

0B

0B

-

IEEE 802.11n AP/Router Network Processor with EEE 14

Track ID: JATR-2265-11 Rev. 0.7

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