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RTL8196

IEEE 802.11n AP/ROUTER NETWORK PROCESSOR WITH EEE

Realtek Semiconductor 

RTL8196C

Datasheet

1. General Description

The RTL8196C is an integrated System-on-a-Chip (SoC) Application Specific Integrated Circuit (ASIC)

that implements a basic L2 5-port Ethernet switch and a high performance CPU. The embedded RISC

CPU is an RLX4181, and the clock rate can be up to 400MHz. To improve computational performance, a

16-Kbyte I-Cache, 8-Kbyte D-Cache, 16-K I-MEM, and 8-Kbyte D-MEM are provided. A standard 5-

signal P1149.1 compliant EJTAG test interface is supported for CPU testing and software development.

The RTL8196C provides five ports (from port 0 to port 4), integrated with five MAC and five physical

layer transceivers for 10Base-T and 100Base-TX. Each port of the RTL8196C may be configured as a

LAN or WAN port.

The RTL8196C supports flexible IEEE 802.3x full-duplex flow control and optional half-duplex

backpressure control. For full-duplex, standard IEEE 803.3x flow control will enable pause ability only

when both sides of UTP have auto-negotiation ability and have enabled pause ability. The RTL8196C

also provides optional forced mode IEEE 802.3x full-duplex flow control. Based on optimized packet

memory management, the RTL8196C is capable of Head-Of-Line blocking prevention.

k L2 Switch Features: The RTL8196C contains a 1024-entry address look-up table with a 10-bit 4-way

XOR hashing algorithm for address searching and learning. Auto aging of each entry is provided and the

lte aging time is 300~450 seconds.

The RTL8196C supports IEEE 802.3az Draft 2.0, also known as Energy Efficient Ethernet (EEE). IEEE

L 802.3az operates with the IEEE 802.3 Media Access Control (MAC) Sublayer to support operation in

a IA Low Power Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on both

sides of the link to save power. Green Ethernet power saving provides: link-on and dynamic detection of

T cable length, and dynamic adjustment of power required for the detected cable length. This feature

e N N provides high performance with minimum power consumption. The RTL8196C also implements link-

R E IO down power saving on a per-port basis, greatly cutting power consumption when the network cable is

disconnected.

ID AT For peripheral interfaces, one 16550-compatible UART is supported, and a 16-byte FIFO buffer is

R provided. A USB 2.0 host controller is embedded in the RTL8196C to provide EHCI and OHCI 1.1

F O compliant host functionality. A USB PHY is also embedded in the RTL8196C.

N RP An MDI/MDIX auto-crossover function is supported. For accessing high-speed devices, the RTL8196C

O O provides a PCI Express bridge to access a PCI Express interface.

C C The RTL8196C requires only a single 25MHz crystal or 40MHz clock input for the system PLL. The

E RTL8196C also has two hardware timers and one watchdog timer to provide accurate timing and

T watchdog functionality. For extension and flexibility, the RTL8196C has up to 17 GPIO pins.

for Z The RTL8196C is provided in a PQFP 128-pin package. It requires only a 3.3V and 1.0V external power

supply.

IEEE 802.11n AP/Router Network Processor with EEE 1

Track ID: JATR-2265-11 Rev. 0.7

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