FAN5236MTC Ver la hoja de datos (PDF) - Fairchild Semiconductor
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FAN5236MTC Datasheet PDF : 20 Pages
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PRODUCT SPECIFICATION
FAN5236
CLK
VDDQ
VTT
Figure 8. Noise-susceptible In-Phase operation for DDR2
These problems are nicely solved by delaying the 2nd con-
verter’s clock by 90° as shown in Figure 9. In this way, all
switching transitions in one converter take place far away
from the decision points of the other converter.
CLK
VDDQ
VTT
Figure 9. Optimal 90° phasing for DDR2
Initialization and Soft Start
Assuming EN is high, FAN5236 is initialized when VCC
exceeds the rising UVLO threshold. Should VCC drop
below the UVLO threshold, an internal Power-On Reset
function disables the chip.
The voltage at the positive input of the error amplifier is lim-
ited by the voltage at the SS pin which is charged with a 5µA
current source. Once CSS has charged to VREF (0.9V) the
output voltage will be in regulation. The time it takes SS to
reach 0.9V is:
T0.9
=
-0---.-9-----×----C-----S---S-
5
(1)
When SS reaches 1.5V, the Power Good outputs are enabled
and hysteretic mode is allowed. The converter is forced into
PWM mode during soft start.
Operation Mode Control
The mode-control circuit changes the converter’s mode of
operation from PWM to Hysteretic and visa versa, based on
the voltage polarity of the SW node when the lower MOS-
FET is conducting and just before the upper MOSFET turns
on. For continuous inductor current, the SW node is negative
when the lower MOSFET is conducting and the converters
operate in fixed-frequency PWM mode as shown in Figure
10. This mode of operation achieves high efficiency at nomi-
nal load. When the load current decreases to the point where
the inductor current flows through the lower MOSFET in the
‘reverse’ direction, the SW node becomes positive, and the
mode is changed to hysteretic, which achieves higher effi-
ciency at low currents by decreasing the effective switching
frequency.
To prevent accidental mode change or "mode chatter" the
transition from PWM to Hysteretic mode occurs when the
SW node is positive for eight consecutive clock cycles (see
Figure 10). The polarity of the SW node is sampled at the
end of the lower MOSFET’s conduction time. At the transi-
tion between PWM and hysteretic mode both the upper and
lower MOSFETs are turned off. The phase node will ‘ring’
based on the output inductor and the parasitic capacitance on
the phase node and settle out at the value of the output volt-
age.
The boundary value of inductor current, where current
becomes discontinuous, can be estimated by the following
expression.
ILOAD(DIS)
=
(---V----I--N-----–-----V----O----U----T---)--V-----O----U----T-
2FSWLOUTVIN
(2)
where T0.9 is in seconds if CSS is in µF.
VCORE
IL
0
VCORE
IL 0
PWM Mode
12345678
Hysteretic Mode
Hysteretic Mode
1
2
3
4
5
6
7
Figure 10. Transitioning between PWM and Hysteretic Mode
PWM Mode
8
10
REV. 1.1.9 7/12/04
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