XR16C872 Ver la hoja de datos (PDF) - Exar Corporation

Número de pieza

componentes Descripción

Lista de partido

XR16C872

Dual UART with 1284 Parallel Port and Plug-and-Play Controller

Exar Corporation 

XR16C872

Preliminary

7.3728 MHz.

Clock from Osc. &

Divider

Pre-scaler

Divides

by 1

Pre-scaler

Divides

by 4

DLM and DLL

Registers

MCR

Bit-7=0

(default)

Baud Rate

Generator

MCR

Bit-7=1

Baud Clock to

Transmitter and

Receiver

Figure 6. Clock Pre-scaler and Baud Rate Generator Circuitry

The generator divides the input 16X clock by any

divisor from 1 to 216 -1. The UART divides the input

clock by 16. Further division of this 16X clock provides

two table rates to support low and high data rate

applications using the same system design. The two

rate tables are selectable through the internal register,

MCR bit-7. Setting MCR bit-7 to logic 1 provides an

additional divide by 4 whereas, setting MCR bit-7 to

logic 0 only divides by 1. (See Table 3 and Figure 6).

The frequency of the internal sampling rate is exactly

16X (16 times) of the selected baud rate. Customized

Baud Rates can be achieved by selecting the proper

divisor values for the MSB and LSB sections of baud

rate generator.

Programming the Baud Rate Generator Registers DLM

(MSB) and DLL (LSB) provides the user capability for

selecting the desired serial baud rate. Table 3 shows

the two selectable baud rate tables available with the

7.3728 MHz clock. The output data rate tolerance is

determined by the frequency accuracy of the

22.1184MHz crystal or external clock.

DMA Operation

The FIFO trigger level provides additional flexibility to

the user for data block transfer operation. LSR bits 5-

6 provide an indication when the transmitter is empty

or has an empty location(s). The user can optionally

operate the transmit and receive FIFOs in the DMA

mode (FCR bit-3). When transmit and receive FIFOs

are enabled and the DMA mode is deactivated (DMA

Mode “0”), the UART activates the interrupt output pin

for each data transmit or receive operation. When DMA

mode is activated (DMA Mode “1”), the user takes the

advantage of block mode operation by loading or

unloading the FIFO in a block sequence determined by

the preset trigger level. In this mode, the UART asserts

the interrupt output pin when characters in the transmit

FIFOs are below the transmit trigger level, or the

number of characters in the receive FIFOs are above

the receive trigger level. Transmit or receive DMA

operation is selected by EMSR register bit 2.

Sleep Mode

The UARTs are designed to operate with low power

consumption. A sleep mode is included to further

reduce power consumption when the chip is not being

used. The operating parameters are maintained while

in sleep. With EFR bit-4 and IER bit-4 enabled (set to

logic 1), the UART enters the sleep mode when no

interrupt is pending and no activities on the modem

port. If an external clock is supplied to the UART, you

Rev. P1.00

22

Share Link: