XR16C872 Ver la hoja de datos (PDF) - Exar Corporation

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XR16C872

Dual UART with 1284 Parallel Port and Plug-and-Play Controller

Exar Corporation 

Preliminary

XR16C872

FIFO Control Register (FCR)

This register is used to enable the FIFOs, clear the

FIFOs, set the transmit/receive FIFO trigger levels,

and select the DMA mode. The DMA, and FIFO modes

are defined as follows:

DMA MODE

Mode 0 - Set and enable the interrupt for each single

character transmit or receive operation. Transmit

empty interrupt will be generated whenever the Trans-

mit Holding Register (THR) is empty and receive ready

interrupt will be generated whenever the Receive Hold-

ing Register (RHR) is loaded with a character. How-

ever, the RX FIFO continues to receive data up to its

limit.

Mode 1 - Enable the interrupt in a block transfer mode

operation. The transmit empty interrupt is set when the

transmit FIFO trigger level is reached. The receive

interrupt is set when the receive FIFO fills up to the

programmed trigger level. However the FIFO continues

to fill regardless of the programmed level until the FIFO

is completely full.

FCR BIT-3:

Logic 0 = Set DMA mode “0”. (normal default condition)

Logic 1 = Set DMA mode “1.”

Transmit operation in mode “0”:

This selects single character interrupt operation. The

transmit empty interrupt will be set when the UART is

set in this 16C450 or single character simulation mode

(FIFOs disabled, FCR bit-0 = logic 0) or in the FIFO

mode (FIFOs enabled, FCR bit-0 = logic 1, FCR bit-3

= logic 0) and when there are no characters in the

transmit FIFO or transmit holding register.

Receive operation in mode “0”:

When the UART is in mode “0” (FCR bit-0 = logic 0) or

in the FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic

0) and there is a character in RHR, the receive ready

interrupt is generated.

Receive operation in mode “1”:

When the UART is in FIFO mode (FCR bit-0 = logic 1,

FCR bit-3 = logic 1) and the receive trigger level has

been reached, or a Receive Time Out has occurred, the

receive ready interrupt is generated.

FCR BIT-0:

Logic 0 = Disable the transmit and receive FIFO.

(normal default condition)

Logic 1 = Enable the transmit and receive FIFO.

This bit must be a “1” when other FCR bits are

written to or they will not be programmed.

FCR BIT-1:

Logic 0 = No FIFO receive reset. (normal default

condition)

Logic 1 = Clears the FIFO counter and resets the

pointers logic (the receive shift register is not cleared

or altered). This bit will return to a logic 0 after clearing

the FIFO.

FCR BIT 4-5: (logic 0 or cleared is the default condition,

TX trigger level = none)

The XR16C850 provide 4 user selectable trigger levels,

The FCTR Bits 4-5 selects one of the following table.

These bits are used to set the trigger level for the

transmit FIFO interrupt. The UART will issue a transmit

empty interrupt when number of characters in FIFO

drops below the selected trigger level.

FCR BIT-2:

Logic 0 = No FIFO transmit reset. (normal default

condition)

Logic 1 = Clears the FIFO counter and resets the

pointers logic (the transmit shift register is not cleared

or altered). This bit will return to a logic 0 after clearing

the FIFO.

Rev. P1.00

29

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