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A416316B

64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

AMIC Technology 

AC Characteristics (continued)

(VCC = 5V ± 10%, VSS = 0V, Ta = 0°C to +70°C)

Std

# Symbol

Parameter

55

tOEH

OE Command Hold Time

56

tCPT

CAS Precharge Time

( CAS -before- RAS Counter Test)

A416316B Series

-30

-35

-40

Unit Notes

Min. Max. Min. Max. Min. Max.

0

-

0

-

0

-

ns

20

-

20

-

20

-

ns

Notes:

1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.

2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.

3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is

achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of 8

RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than

8ms).

4. AC Characteristics assume tT = 3ns. All AC parameters are measured with a load equivalent to one TTL loads and

50pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC.

5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured

between VIH and VIL.

6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference

point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.

7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference

point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.

8. Assumes three state test load (5pF and a 380Ω Thevenin equivalent).

9. Either tRCH or tRRH must be satisfied for a read cycle.

10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output

voltage levels.

11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet

as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle

and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥

tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from

the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is

indeterminate.

12. These parameters are referenced to UCAS and LCAS leading edge in early write cycles and to WE leading edge in

read-modify-write cycles.

13. Access time is determined by the longer of tAA or tCAC or tCPA.

14. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.

15. These parameters are sampled and not 100% tested.

PRELIMINARY (November, 2000, Version 0.0)

9

AMIC Technology, Inc.

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