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AX88140A

Fast Ethernet MAC Controller

Unspecified 

AX88140A

PRELIMINARY

4.0 Registers Operation

1. The REGs are quad-word aligned, 32-bits long, and must be accessed using long-word

instruction with quad-word aligned addresses only.

2. Reserved bits should be written with 0.; Reserved bits are UNPREDICTABLE on read

access.

3. Retries on second data transactions occur in response to burst accesses.

4.1 Registers Mapping

REGISTER

MEANING

REG0

REG1

REG2

REG3

REG4

REG5

REG6

REG7

REG8

REG9

REG10

REG11

REG12

REG13

REG14

BUS MODE

TRANSMIT POLL DEMAND

RECEIVE POLL DEMAND

RECEIVE LIST BASE ADDRESS

TRANSMIT LIST BASE ADDRESS

STATUS

OPERATION MODE

INTERRUPT ENABLE

MISSED FRAME AND OVERFLOW COUNTER

SERIAL ROM, AND MII MANAGEMENT

-

GENERAL-PURPOSE TIMER

GENERAL-PURPOSE PORT

FILTERING BUFFER INDEX

FILTERING BUFFER DATA

OFFSET FROM REG BASE ADDRESS

(CBIO,CBMA)

00H

08H

10H

18H

20H

28H

30H

38H

40H

48H

50H

58H

60H

68H

70H

Tab - 14 Command and Status Register Mapping

20

ASIX ELECTRONICS CORPORATION

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