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CXA1616N

Sync Discriminator for CRT Displays

Sony Semiconductor 

CXA1616N/S

Pin Description

Pin No.

Symbol Pin voltage

SDIP SSOP

Equivalent circuit

(Ta = 25°C, VCC = 12V)

Description

1 1 VS IN

VCC

200k

Inputs the vertical separate sync.

Inputs at TTL level and polarity is

positive/negative.

—

1k

1

8k

V Low ≤ 0.5V

V High ≥ 4.5V

20k

Connect a pull-down resistance of

8k

470kΩ or less to GND.

2 2 PVC

5 5 PHC

VCC

0.3, 3.4V 2

48k

96k

1k

32k

8k

32k

Connection pin of an integral capacitor

for the polarity discriminator circuit

(Polarity Check); connects a 0.22µF

capacitor to GND.

When the capacitor is connected at

positive polarity: 3.4V;

negative polarity: 0.3V.

No input : 3.7V.

3 3 EVC

VCC

5V

4.3 to 7.9V 3

8k

Vertical ramp waveform generator.

Generates a ramp waveform

synchronized to the input separate

sync frequency. Connects a 0.68µF

capacitor to GND.

The charging time constant (rising

48k

edge) of ramp waveform is determined

by the 2kΩ resistance and the external

0.68µF capacitor, and the discharging

2k

time constant (falling edge) by the

external 0.68µF capacitor and the

internal 17µA current.

32k

When there is a verticai separate

17µA sync, the voltage at Pin 3 rises

between 5.5 and 7.9V, existence

discrimination (Exist Check) is

performed, and an input signal is

judged to exist.

The voltage is 4.3V when no input

signal exists.

4 4 CS IN

4.2V

VCC

72k

200

4

400k

2k 100µA

Inputs the composite and horizontal

separate sync (positive/negative

polarity). Amplitude is 1 to 5Vp-p. Input

through a capacitor.

4V

–3–

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