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DM9102D

Single Chip Fast Ethernet NIC Controller

Davicom Semiconductor, Inc. 

Bit

Default

31

0

30

0

29

0

28

0

27

0

26:25

01

24

0

23

0

22

0

21

0

20

1

19:10

0

9

0

8

0

7

0

6

0

Final

Version: DM9102D-DS-F01

May 10, 2006

Type

R/C

R/C

R/C

R/C

R/C

R/C

R/C

RO

RO

RO

RO

RO

RO

RW

RO

RW

Description

Detected Parity Error

The DM9102D samples the AD[0:31], C/BE[0:3]#, and the PAR signal to

check parity and to set parity errors. In slave mode, the parity check falls

on command phase and data valid phase (IRDY# and TRDY# both

active). In master mode, the DM9102D will check each data phase, during

a memory read cycle, for parity error. During a memory write cycle, if an

error occurs, the PERR# signal will be driven by the target. This bit is set

by the DM9102D and cleared by writing "1". There is no effect by writing

"0"

Signal For System Error

This bit is set when the SERR# signal is driven by the DM9102D. This

system error occurs when an address parity is detected under the

condition that bit 8 and bit 6 in command register below are set

Master Abort Detected

This bit is set when the DM9102D terminates a master cycle with the

master-abort bus transaction

Target Abort Detected

This bit is set when the DM9102D terminates a master cycle due to a

target-abort signal from other targets

Send Target Abort (0 for No Implementation)

The DM9102D will never assert the target-abort sequence

DEVSEL Timing (01 Select Medium Timing)

Medium timing of DEVSEL# means the DM9102D will assert DEVSEL#

signal two clocks after FRAME# is sample “asserted”

Data Parity Error Detected

This bit will take effect only when operating as a master and when a Parity

Error Response Bit in command configuration register is set. It is set under

two conditions:

(i) PERR# asserted by the DM9102D in memory data read error

(ii) PERR# sent from the target due to memory data write error

Slave Mode Fast Back-To-Back Capable (0 for No Support)

This bit is always reads "1" to indicate that the DM9102D is capable of

accepting fast back-to-back transaction as a slave mode device

User-Definable Feature Supported (0 for No Support)

66 MHz (0 for No Capability)

New Capability

This bit indicates whether this function implements a list of extended

capabilities such as PCI power management. This bit may be updated by

EEPROM. When set this bit indicates the presence of New Capability. A

value of 0 means that this function does not implement New Capability

Reserved

Master Mode Fast Back-To-Back (0 for No Support)

The DM9102D does not support master mode fast back-to-back

capability and will not generate fast back-to-back cycles

SERR# Driver Enable/Disable

This bit controls the assertion of SERR# signal output. The SERR# output

will be asserted on detection of an address parity error and if both this bit

and bit 6 are set

Address/Data Stepping (0 for No Stepping)

Parity Error Response Enable/Disable

13

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