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BT869KRF

Flicker-Free Video Encoder with Ultrascale™ Technology

Conexant Systems 

1.0 Functional Description

1.1 Pin Descriptions

Table 1-1. Pin Assignments (1 of 3)

Pin Name I/O

Pin #

XTALIN

XTALOUT

I 63

O 62

VDD_X

VSS_X

— 61

— 64

VAA_PLL

— 59

AGND_PLL

— 58

CLKO

O 56

VDD_CO

VSS_CO

CLKI

— 57

— 55

I 54

RESET*

I 53

SLEEP

SLAVE

PAL

VDDMAX

ALTADDR

I 52

I 51

I 50

I 49

I 48

SIC

SID

VDD_SI

I 45

I/O 44

— 47

1-2

Bt868/Bt869

Flicker-Free Video Encoder with UltrascaleTM Technology

Description

A crystal can be connected to these pins. The pixel clock output (CLKO) is

derived from these pins with a PLL. XTALIN can be driven as a CMOS input

pin.

Crystal oscillator supply pin. This pin should be tied to the digital supply.

Crystal oscillator ground pin. This pin should be tied to the digital ground

plane.

Analog power for PLL. All VAA and VDD pins must be connected together on

the same PCB plane to prevent latchup.

Analog ground for PLL. All AGND and VSS pins must be connected together

on the same PCB plane to prevent latchup.

Pixel clock output (TTL compatible). This pin is three-state if the CLKI pin

provides the encoder clock.

Clock output supply pin. This pin should be tied to the digital supply.

Clock output ground pin. This pin should be tied to the digital ground plane.

Pixel clock input (TTL compatible). This may be used as either the encoder

clock or a delayed version of the CLKO pin synchronized with the pixel data

input.

Reset control input (TTL compatible). A logical 0 resets and disables video

timing (horizontal, vertical, subcarrier counters to the start of VSYNC of first

field) and resets the serial interface registers). RESET* must be a logical 1

for normal operation.

Power-down control input (TTL compatible). A logical 1 configures the

device for power-down mode. A logical 0 configures the device for normal

operation.

Slave/master mode select input (TTL compatible). A logical 1 configures the

device for slave video timing operation. A logical 0 configures the device for

master video timing operation.

PAL/NTSC mode select input (TTL compatible). A logical 1 configures the

device for PAL video format and Mode 1. A logical 0 configures the device

for NTSC video format and Mode 0.

Input threshold adjustment. This pin should be tied to VDD for 3.3 V input

swings and GND for 5 V input swings. This pin does not affect the serial

interface pins (SID and SIC).

Alternate slave address input (TTL compatible). A logical 0 configures the

device to respond to a serial programming address of 0x88; a logical 1

configures the device to respond to a serial programming address of

0x8A.(1)

Serial interface clock input (TTL compatible). The maximum clock rate is

400 kHz.

Serial interface data input/output (TTL compatible). Data is written to and

read from the device via this serial bus.

Serial interface input supply pin. This pin should be tied to the proper supply

voltage for the desired serial interface operating voltage (i.e., tie to 5 V for

5 V serial interface compatibility).

Conexant

100123B

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