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ICS1522

User-ProgrammableVideo Clock Generator/ Line-Locked Clock Regenerator

Integrated Circuit Systems 

ICS1522

Overview

The ICS1522 is ideally suited to provide the graphics

system clock signals required by high-performance video

DACs. Fully programmable feedback and reference divider

capability allow virtually any frequency to be generated,

not just simple multiples of the reference frequency. The

ICS1522 uses the latest generation of frequency synthesis

techniques developed by ICS and is completely suitable

for the most demanding video applications.

PLL Synthesizer Description -

Ratiometric Mode

The ICS1522 generates its output frequencies using phase-

locked loop techniques. The phase-locked loop (or PLL) is

a closed-loop feedback system that drives the output

frequency to be ratiometrically related to the reference

frequency pro-vided to the PLL (see Block Diagram). The

reference frequency is generated by an on-chip crystal

oscillator or the reference frequency may be applied to the

ICS1522 from an external frequency source, typically

horizontal sync from another dis-play system.

The phase-frequency detector shown in the Block Diagram

drives the voltage-controlled oscillator, or VCO, to a

frequency that will cause the two inputs to the phase-

frequency detector to be matched in frequency and phase.

This occurs when:

F(VCO): = F(XTAL1) . Feedback Divider

Reference Divider

This expression is exact; that is, the accuracy of the output

frequency depends solely on the reference frequency

provided to the part (assuming correctly programmed

dividers).

The VCO gain is programmable, which permits the ICS1522

to be optimized for best performance at all operating fre-

quencies.

The feedback divider may be programmed for any modulus

from 64 to 2048 in steps of one followed by a divide by 1,

2, 4 or 8 feedback post-scaler.

The reference divider may be programmed for any modulus

from 1 to 1024 in steps of one.

Output Post-scaler

A programmable post-scaler may be inserted between the

VCO and the CLK+ and CLK- outputs of the ICS1522. This

is useful in generating of lower frequencies, as the VCO

has been optimized for high-frequency operation.

The post-scaler allows the selection of dividing the VCO

frequency by either 1, 2, 4 or 8.

Load Clock Divider

The ICS1522 has an additional programmable divider

(referred to in the Block Diagram as the load counter) that

is used to generate the LOAD clock frequency for the

video DAC. The modulus of this divider may be set to 3, 4,

5, 6, 8, or 10 under register control. The design of this

divider permits the output duty factor to be 50/50, even

when odd modulus is selected. The input frequency to this

divider is the output of the output post-scaler described

above.

Digital Inputs - ICS1522

The programming of the ICS1522 is performed serially by

using the SDATA, SCLK, and SELn pins to load the 7, 11

bit internal memory locations.

Single bit changes are accomplished by addressing the

appro-priate memory location and writing only 11 bits of

data, not by writing all 77 data bits.

For proper programming of the ICS1522, it is important

that all transitions of the SELn input occur during the same

state of the SCLK input.

SDATA is shifted into a 15 bit serial register on the rising

edge of SCLK while SELn is low. The first bit loaded is R/

Wn followed by a 3 bit address and 11 bit data (both

address & data are LSB first). When a rising edge of SCLK

occurs while SELn is high (SDATA ignored), the contents

of the serial register are loaded into the addressed 11 bit

memory location if R/Wn is low. If R/Wn is high upon the

above condition, the data from the addressed memory

location is loaded into the serial shift register and SDATA

is set as an output. The 3 bit address and 11 bit data will be

serially shifted out of the ICS1522 on the SDATA pin on

the rising edge of SCLK while SELn is low (see Timing

Diagram).

An additional control pin on the ICS1522, PDEN can be

used to disable the phase-frequency detector in line-locked

applica-tions. When disabled, the phase detector will ignore

any inputs and allow the VCO to coast. This feature is

useful in systems using composite sync.

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