ICS1522 Ver la hoja de datos (PDF) - Integrated Circuit Systems

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ICS1522

User-ProgrammableVideo Clock Generator/ Line-Locked Clock Regenerator

Integrated Circuit Systems 

ICS1522

REG#

6

6

6

6

6

6

6

6

BIT(S)

3

4

5

6

7

8

9

10

BIT REF.

OMUX1

OMUX2

OMUX3

OMUX4

DACRST

AUXEN

AUXCLK

EXTREF

DESCRIPTION

OUT1 Select (Default=0)

0=Load Counter Output 1=Diff.

Output Divided by 4 at 0 Degrees

OUT1 will track OMUX1 when AUXEN=1

OUT2 Select (Default=0)

0=Internal Feedback Pulse 1=Diff.

Output Divided by 4 at 90 Degrees

OUT2 will track OMUX2 when AUXEN=1\

OUT3 Select (Default=0)

0=Feedback Sync Pulse LO

1=Diff. Output Divided by 4 at 180

Degrees OUT3 will track OMUX3 when AUXEN=1

OUT4 Select (Default=1)

0=Feedback Sync Pulse HI

1=Diff. Output Divided by 4 at 270 Degrees

OUT4 will track OMUX4 when AUXEN=1

Output Reset (Default=0)

When set to one, the CLK+ output is

kept high and the CLK-output is kept low. When returned to zero,

the CLK+ and CLK-outputs will resume toggling on a rising edge

of the OUT1 output (programmed for Load Counter) within +/- 1

clock period.

Output Test Mode (Default=0)

0=Normal Output Operation

1=Output Test Mode (see OMUX1-4 and AUXCLK)

Output Clock when in Test Mode (Default=0)

CLK+ and CLK- will track AUXCLK when AUXEN=1

XTAL/EXTREF Input Buffer (Default=0)

0=Crystal Input Operation

1=External Reference Input Operation

8

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