LV71081E Ver la hoja de datos (PDF) - SANYO -> Panasonic
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LV71081E Datasheet PDF : 31 Pages
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Serial Control Specification
1. Slave address
MSB
1
0
0
1
0
LV71081E
LSB
1
0
0
Slave receiver
One-way communication (this IC is dedicated to receive)
2. DATA TRANSFER MANUAL : [1] is High level. [0] is Low level.
I2C-BUS control system is adopted in SW LSI. SW LSI is controlled by SCL (Serial Clock) and SDA (Serial Data) At
first, please set up the START condition*1 by these two terminals (SCL and SDA). And next, please input the 8bits data,
which should be synchronized with SCL into SDA terminal. Still more, please give priority to high rank bit at data
transfer order (MSB→LSB). The 9th bit is called as ACK (Acknowledge), SW LSI sends [0] to the SDA terminal
during SCL [1] period. So, please open the port of microprocessor during this period. LV71081E adopt auto-increment,
so you input only first group-address and you can transfer data in order. As thus the Data transfer Stop condition*2 is
finished.
*1 SDA rise up during SCI is [1]
*2 SDA fall down during SCL is [1]
3. TRANSFER DATA FORMAT
The transfer data is composed by START condition, Slave address, Group address*1, data, and STOP condition.
After setting up the START condition, please transfer the Slave Address (regulated as “1001000” in SW LSI). Group
and next control data*2 (Please see the Fig.1)
Slave Address is composed by 7bits, and this bit 8th bit*3 should be set as [0].
The both of Group address and control data are composed by 8bits, and the one control action is defined with
combination of these two data. And if you want to control 2 or more groups at the same mode, you can realize it by
sending some control data together.
The data makes meaning with all bits, so you cannot stop the sending until all data transfer is over.
But LV71081E adopt auto-increment, for example you can stop to transfer STOP condition after group 2 data.
If you want to stop transfer action, please transfer the STOP condition without fail.
*1/2 There are 8 control groups.
*3 This 8th bit called as R/W bit, and this bit shows the data transmission direction. [0] means send mode (accept
mode with SW LSI) and [1] means accept mode (send mode with SW LSI) fundamentally. But SW LSI is not
equipped with such a data out function, please keep this bit as [0].
Fig. 1 DATA STRUCTURE
START condition Slave address R/W ACK Group address ACK Control data ACK .....
STOP condition
Start condition
Acknowledge
Stop condition
No.A1610-15/31
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