LV71081E Ver la hoja de datos (PDF) - SANYO -> Panasonic

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LV71081E

For Video/Audio Signal Input/Output Interface of DVD Recorder

SANYO -> Panasonic 

LV71081E

4. INITIALIZE AND OTHERS

SW LSI is initialized as the following mode for circuit protection. Please see “SERIAL CONTROL TABLE”.

Characteristics of the SDA and SCL 1/0 stages for SW LSI

Parameter

LOW level input voltage

HIGH level input voltage

LOW level output current

SCL clock frequency

Set-up time for a repeated START condition

Hold time START condition. After this period, the first clock pulse is generated.

LOW period of the SCL clock

Rise time of both SDA and SDL signals

HIGH period of the SCL clock

Fall time of both SDA and SDL signals

Data hold time:

Data set-up time

Set-up time for STOP condition

BUS fredd time between a STOP and START condition

Symbol

VIL

VIH

IOL

fSCL

tSU : STA

tHD : STA

tLOW

tR

tHIGH

tF

tHD : DAT

tSU : DAT

tSU : STO

tBUF

Min

0

3.0

0.6

0.6

1.3

0

0.6

0

0

100

0.6

1.3

Max

Unit

0.8

V

5.0

V

3.0

mA

400

kHz

μs

μs

μs

0.3

μs

μs

0.3

μs

0.9

μs

ns

μs

μs

Fig.2 Definition of timing.

SCL (86pin)

tSU:STA

SDA (87pin)

tLOW

tHD:STA

tHIGH

tR

tHD:DAT

tF

tSU:DAT

tSU:STO tBUF

No.A1610-16/31

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