![](/html/Siemens/766070/page237.png)
PSB 4860
Electrical Characteristics
MA0-MA13
RAS
CAS0,CAS1
MD0-MD7
row addr.
t1
t2
col. addr.
t4
t3
t5
t6
t7 t8
Figure 76 Memory Interface - DRAM Read Access
Parameter
Symbol Limit values
Unit
Memory Interface - DRAM Read Access
Min
Max
row address setup time
t1
50
ns
row address hold time
t2
50
ns
column address setup time
t3
50
ns
RAS precharge time
t4
110
ns
RAS to CAS delay
t5
110
2000 ns
CAS pulse width
t6
110
2000 ns
Data input setup time
t7
40
ns
Data input hold time
t8
0
ns
Semiconductor Group
237
10.97