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TMC22071A

Genlocking Video Digitizer

Cadeka Microcircuits LLC. 

PRODUCT SPECIFICATION

TMC22071A

GVSYNC and GRS data will continue. The GRS data will

be the initial subcarrier frequency and phase values selected

by the Format select bits of the Control Register. The

TMC22071A will acquire and lock to incoming video within

two frames after video is restored.

Subcarrier Phase-Locked Loop

A fully-digital phase-locked loop is used to extract the phase

and frequency of the incoming color burst. These frequency

and phase values are output over the CVBS bus during the

horizontal sync period. Fairchild’s video decoder and gen-

lockable encoder chips will accept these data directly.

Back Porch Digital Clamp

A digital back-porch clamp is employed to ensure a constant

blanking level. It digitally offsets the data from the A/D con-

verter to set the back porch level to precisely 3Ch for NTSC

and 40h for PAL. When the digital clamp is enabled, the

CVBS video output data is determined from the A/D conver-

sion result minus the back porch level + 3Ch (40h for PAL).

Digitized Video Output

The digitized 8-bit video output is provided over an 8-bit

wide CVBS data port, synchronous with PXCK and LDV.

Subcarrier frequency, subcarrier phase, and Field ID data

(GRS) are transmitted in 4-bit nibbles over CVBS3-0 during

the horizontal sync tip period at the PXCK rate.

Microprocessor Interface

Since microprocessor buses are notoriously noisy from a

wide-band analog point of view, the microprocessor inter-

face bus is only one bit wide, rather than the more customary

eight. The operation of this bus is similar to other bus-

controlled devices except that the TMC22071A internal

Control Register is accessed one bit at a time.

A sequence of 47 bits is written to or read from the LSB of a

standard microprocessor port. Writing to or reading from the

secondary address results in the transfer of data to or from

the internal shift register.

The RESET input, when LOW, sets all internal state

machines to their initialized conditions. Returning the

RESET pin HIGH starts the signal acquisition sequence

which lasts until locking with the gain-adjusted and clamped

video signal is achieved.

Pin Assignments

1 68

65-22071-02

Pin Name

1 VDD

2 CVBS0

3 CVBS1

4 CVBS2

5 CVBS3

6 CVBS4

7 VDD

8 DGND

9 CVBS5

10 CVBS6

11 CVBS7

12 GHSYNC

13 GVSYNC

14 VALID

15 DGND

16 DGND

17 LDV

Pin Name

18 VDD

19 PXCK

20 DGND

21 DGND

22 VDD

23 VDDA

24 AGND

25 VDDA

26 VDDA

27 AGND

28 RB

29 VIN3

30 VDDA

31 VIN2

32 AGND

33 VDDA

34 VIN1

Pin Name

35 AGND

36 RT

37 AGND

38 VREF

39 AGND

40 VDDA

41 AGND

42 CBYP

43 PFD IN

44 AGND

45 DDS OUT

46 PXCK SEL

47 VDDA

48 COMP

49 AGND

50 DGND

51 CLK IN

Pin Name

52 VDD

53 CLK OUT

54 EXT PXCK

55 DGND

56 DGND

57 DGND

58 VDD

59 VDD

60 A0

61 R/W

62 CS

63 VDD

64 RESET

65 DGND

66 D0

67 INT

68 DGND

3

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