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GS1522-CQR
(Rev.:2000)

HDTV Serial Digital Serializer

Gennum -> Semtech 

charge pump drops with reducing data transitions. During

pathological signals, the data transition density reduces

from 0.5 to 0.05, but the slew PLL’s performance does not

change significantly.

Because most of the PLL circuitry is digital, it is very robust

like other digital systems which are generally more robust

than their analog counterparts. Additionally, signals like DM

(86), which represents the internal functionality, can be

generated without adding additional artifacts. Thus, system

debugging is also possible with these features. The

complete slew PLL is made up of several blocks including

the phase detector, the charge pump and an external

Voltage Controlled Oscillator (VCO).

0.2

INPUT

0.1

OUTPUT

0.0

SLEW PLL RESPONSE

GS1522 PLL

PCLK_IN

PHASE

DETECTOR

DIVIDE-BY-20

GO1515

VCO

Fig. 15 Phase Lock Loop Frequency Synthesis

7. LOCK LOGIC

Logic is used to produce the PLL_LOCK (15) signal which

is based on the LFS signal and phase lock signal. When

there is not any data input, the integrator will charge and

eventually saturate at either end. By sensing the saturation

of the integrator, it is determined that no data is present. If

either data is not present or phase lock is low, the lock

signal is made low. Logic signals are used to acquire the

frequency by sweeping the integrator. Injecting a current

into the summing node of the integrator achieves the

sweep. The sweep is disabled once phase lock is asserted.

The direction of the sweep is also changed once LFS

saturates at either end.

0.2

INPUT

0.1

OUTPUT

0.0

LINEAR (CONVENTIONAL) PLL RESPONSE

Fig. 14 PLL Characteristics

6. PHASE LOCK LOOP FREQUENCY SYNTHESIS

The GS1522 requires the HDTV parallel clock (74.25 or

74.25/1.001 MHz) to synthesize a serial clock which is 20

times the parallel clock frequency (1.485MHz) using a

phase locked loop (PLL). This serial clock is then used to

strobe the output serial data. Figure 15 illustrates this

operation. The VCO is normally free-running at a frequency

close to the serial data rate. A divide-by-20 circuit converts

the free running serial clock frequency to approximately that

of the parallel clock. Within the phase detector, the divided-

by-20 serial clock is then compared to the reference

parallel clock from the PCLK_IN pin (2). Based on the

leading or lagging alignment of the divided clock to the

input reference clock, the serial data output is synchronized

to the incoming parallel clock. The following sections

describe the functional blocks in greater detail.

8. PHASE DETECTOR

The phase detector portion of the slew PLL used in the

GS1522 is a bi-level digital phase detector. It indicates

whether the data transition occurred before or after with

respect to the falling edge of the internal clock. When the

phase detector is locked, the data transition edges are

aligned to the falling edge of the clock. The input data is

then sampled by the rising edge of the clock, as shown in

Figure 16. In this manner, the allowed input jitter is 1UI p-p

in an ideal situation. However, due to setup and hold time,

the GS1522 typically achieves 0.8UI p-p input jitter

tolerance without causing any errors in this block. When the

signal is locked to the internal clock, the control output from

the phase detector is refreshed at the transition of each

rising edge of the data input. During this time, the phase of

the clock drifts in one direction.

PHASE ALIGNMENT

EDGE

RE-TIMING

EDGE

IN-PHASE CLOCK

INPUT CLOCK

WITH JITTER

0.8UI

GENNUM CORPORATION

OUTPUT DATA

Fig. 16 Phase Detector Characteristics

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