GS1522-CQR(2000) Ver la hoja de datos (PDF) - Gennum -> Semtech
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GS1522-CQR Datasheet PDF : 20 Pages
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PIN DESCRIPTIONS
NUMBER
SYMBOL
1, 95
VEE3
2
3, 4, 5, 6, 7, 8,
9, 11, 12, 14,
19, 20, 32, 33,
34, 35, 36, 37,
38, 39, 40, 41,
42, 43,46, 50,
51, 52, 56, 60,
61, 62, 65, 66,
67, 68, 69, 70,
71, 72, 73, 80,
81, 83, 93, 97,
98, 99, 100,
101, 102, 108,
109, 116, 117,
120, 121
10
PCLK_IN
NC
BUF_VEE
13
XDIV20
15
PLL_LOCK
16
BYPASS
17
RESET
18, 26, 27, 28,
29, 30, 59
21, 22, 23, 24,
25, 45, 57
31
VEE2
VCC2
SDO1_EN
44
47, 49
48, 54
53, 55
RSET1
SDO1+, SDO1-
SDO_NC
SDO0+, SDO0-
LEVEL
Power
TTL
TYPE
Input
Input
DESCRIPTION
Negative Supply. Most negative power supply connection, for
input stage.
Parallel Data Clock. 74.25 or 74.25/1.001MHz
No Connect. These pins are not used internally. These pins
should be floating.
Power
TTL
TTL
TTL
TTL
Power
Power
Power
Analog
Analog
TEST
TEST
Output
Input
Input
Input
Input
Input
Input
Output
Output
Negative Supply/Test Pin. Most negative power supply
connection. For buffer for oscillator/divider for test purposes only.
Leave floating for normal operation.
Test Pin. Test block output. Leave floating for normal operation.
Status Signal Output. Indicates when the GS1522 is phase locked
to the incoming PCLK_IN clock signal. LOGIC HIGH indicates
PLL is in Lock. LOGIC LOW indicates PLL is out of Lock.
Control Signal Input. Used to bypass the scrambling function if
data is already scrambled by GS1501 or if non-SMPTE encoded
data stream such as 8b/10b is to be transmitted. When BYPASS is
LOW, the SMPTE scrambler and NRZ(I) encoder are enabled.
When BYPASS is HIGH, the SMPTE scrambler and NRZ(I) encoder
are bypassed.
Control Signal Input. Used to reset the SMPTE scrambler. For
logic HIGH; Resets the SMPTE scrambler and NRZ(I) encoder.
For logic LOW: normal SMPTE scrambler and NRZ(I) encoder
operation.
Negative Supply. Most negative power supply connection. For
Cable Driver outputs and all other digital circuitry excluding input
stage and PLL stage.
Positive Supply. Most positive power supply connection. For
Cable Driver outputs and all other digital circuitry excluding input
stage and PLL stage.
Control Signal Input. Used to enable or disable the second serial
data output stage. This signal must be tied to GND to enable this
stage. Do not connect to a logic low.
Control Signal Input. External resistor is used to set the data
output amplitude for SDO1 and SDO1. Use a ±1% resistor.
Serial Data Output Signal. Current mode serial data output #1.
Use 75Ω ±1% pull up resistors to VCC2.
No Connect. Not used internally. This pin must be left floating.
Serial Data Output Signal. Current mode serial data output #0.
Use 75Ω ± 1% pull up resistors to VCC2.
5
GENNUM CORPORATION
522 - 26 - 00
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