GS880Z18AT-133 Ver la hoja de datos (PDF) - Unspecified

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GS880Z18AT-133

9Mb Pipelined and Flow Through Synchronous NBT SRAM

Unspecified 

GS880Z18/36AT-250/225/200/166/150/133

Pipeline and Flow Through Read Write Control State Diagram

D

B

Deselect

R

W

D

W

New Read

R

B

R

W

Burst Read

B

D

Key

Input Command Code

ƒ Transition

Current State (n)

Next State (n+1)

n

n+1

Clock (CK)

D

R New Write

W

B

W

R

Burst Write

B

D

Notes:

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B and D represent input command

codes ,as indicated in the Synchronous Truth Table.

n+2

n+3

Command

ƒ

ƒ

ƒ

ƒ

Current State

Next State

Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram

Rev: 1.02 9/2002

8/25

© 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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