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MX98L715BEC Ver la hoja de datos (PDF) - Macronix International

Número de pieza
componentes Descripción
Lista de partido
MX98L715BEC
MCNIX
Macronix International MCNIX
MX98L715BEC Datasheet PDF : 50 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MX98L715BEC
Pin Name Type
VDDA
P
GNDA
G
VDDR
P
GNDR
G
TXE
T/S
( BPD1)
TXD
T/S
( BPD2)
RXD
T/S
( BPD3)
RXC
T/S
( BPD4)
COL
T/S
( BPD5)
CRS
T/S
( BPD6)
TXC
T/S
( BPD7)
CLKRUNB T/S
ISOLATE T/S
Pin No
128 Pin Function and Driver
82, 85, 89, Analog Power pins.
97,103,
83,84,88,96, Analog Ground pins.
100,101,104,
91, 94,105 Receive Channel Power pins.
90, 95,106 Receive Channel Ground pins.
57
Transmit Enable Output : TXE signal in 7 wire interface for Home PNA
connection. ( Or BPD1 pin during Flash or boot ROM activities )
56
Transmit Data Output : TXD signal in 7 wire interface for Home PNA
connection. ( Or BPD2 pin during Flash or boot ROM activities )
55
Receive Data Input : RXD signal in 7 wire interface for Home PNA
connection. ( Or BPD3 pin during Flash or boot ROM activities )
54
Receive Clock Input : RXC signal in 7 wire interface for Home PNA
connection. ( Or BPD4 pin during Flash or boot ROM activities )
53
Collision Input : COL signal in 7 wire interface for Home PNA
connection. ( Or BPD5 pin during Flash or boot ROM activities )
52
Transmit Enable Output : CRS signal in 7 wire interface for Home PNA
connection. ( Or BPD6 pin during Flash or boot ROM activities )
51
Transmit Clock Input : TXC signal in 7 wire interface for Home PNA
connection. ( Or BPD7 pin during Flash or boot ROM activities )
107
Mini PCI bus CLock Run pin : Indicates the MiniPCI clock status, normally
controlled by host, low for normal clocking, high when clock is about to be
slowed down. Can be asserted low by MX98L715BEC to request normal
clocking when necessary.
108
ISOLATE pin : Output pin to isolate external Home PNA PHY chip
P/N:PM0695
REV. 0.3, MAR. 30, 2001
7

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