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CXD1948R

IEEE1394 Link Layer LSI for DVB and DSS

Sony Semiconductor 

Transmit Interface (for sync mode/8 bit/Nbyte)

CXD1948R

AICK

PACKETEN

Don’t Care

AIWRITE

AIDT Don’t Care

ERRFLAG

0

1

2

first data

taken in

second data

taken in

3

········ N – 3 N – 2

Valid interval for transport stream packet

N–1

Don’t Care

Sync interface mode is obtained by setting the CFR AsyncAI register to 0. (The default is 0.)

The CXD1948R identifies the first data of the transport stream packet by detecting that the PACKETEN signal

has gone from low to high.

There is no particular need to input the PACKETEN signal after the first data. The size of the data taken in as

valid data is equal to the value set in the CFR S_PacketSize register, decreased by 4 and by the value set in

the AddSize register. The timing for taking in of the data internally is done by AICK rise when AIWRITE is

high.

The AIWRITE signal is used as the enable signal, so the interval that the AIWRITE signal is high relative to

one data must be one AICK clock interval. The interval that the AIWRITE signal is low relative to one data is

not specified.

The limits on AICK input frequency are given below.

For 8-bit data input: 40MHz (Max.), 2MHz (Min.)

For 16-bit data input: 20MHz (Max.), 2MHz (Min.)

The ERRFLAG input during transmit can be made valid by setting the CFR ErrBitEnable register to 1. (The

default is 0.)

The CXD1948R identifies the subject packet as an error if the ERRFLAG input is high for even one data

during transport stream packet valid interval.

The switching timing for ERRFLAG input can be changed in the same way as data switching timing, with

AIWRITE signal rise.

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