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CXD1948R Ver la hoja de datos (PDF) - Sony Semiconductor

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CXD1948R
Sony
Sony Semiconductor Sony
CXD1948R Datasheet PDF : 78 Pages
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CXD1948R
5-2-6. Using the ERRFLAG Pin
The CXD1948R can function as a transport stream data interface using error information.
Concretely, this is done using the ERRFLAG pin.
Like other transport stream data interfaces, the ERRFLAG pin is a bidirectional pin. I/O switching is performed
by the CFR IGFMode register.
Also, ERRFLAG control is performed by the CFR ErrBitEn and ErrOutEn registers.
The settings when using ERRFLAG during transmit and receive are given below.
Transmit settings
The ERRFLAG input can be made valid by setting the CFR ErrBitEn register to “1”. (The default is “0”.)
In order to add the error information provided by ERRFLAG to an isochronous packet and transmit this
information, the added data must be 4 bytes or more.
Concretely, the CFR AddSize register value must be 4 or larger.
Both of the conditions below must be met to send error information using the ERRFLAG pin during transmit.
(1) The ErrBitEn register is 1.
(2) The AddSize register is 4 or higher.
Receive settings
The ERRFLAG output can be made valid by setting the CFR ErrOutEn register to “1”. (The default is “0”.)
The CXD1948R handles received packet errors in two ways as follows.
(1) Packets with error information added to the transport stream data
In this case, the error information must be added to the received isochronous packet.
In addition, the CFR ErrBitEn register must be set to 1.
(2) Error packets occurring during isochronous communication
These errors refer to packets received with non-consecutive DBC values due to CRC errors or Late
processing during transmit.
In this case, only the CFR ErrOutEn register is set.
Setting this register to “1” inserts an error packet between packets with non-consecutive DBC values.
As a result, one packet of ERRFLAG = 1 data is read by the transport stream data interface.
If the ErrOutEn register is set to 0, this processing is not performed.
Non-consecutive DBC values also result when the receive FIFO overflows, and the processing is the same
in these cases as well.
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