78Q2120 Ver la hoja de datos (PDF) - TDK Corporation

Número de pieza

componentes Descripción

Lista de partido

78Q2120

10/100BASE-TX Ethernet Transceiver

TDK Corporation 

78Q2120

10/100BASE-TX

Ethernet Transceiver

MR0 - CONTROL REGISTER (continued)

BIT

SYMBOL

TYPE

0.8

DUPLEX

R, W, (1)

0.7

COLT

R, W, 0

0.6:0

RSVD

R, 0

DESCRIPTION

DUPLEX MODE: This bit determines whether the 78Q2120

supports full duplex or half duplex. A logic one indicates full duplex

operation and a logic zero indicates half duplex. When auto-

negotiation is enabled, this bit will have no effect on the 78Q2120.

At reset, this bit reflects the highest operating mode allowed by the

TECH [2:0] pins. The MII can write to this bit, but the bit will change

value only if the new value is allowed by the TECH pins.

COLLISION TEST: When this bit is set to one, the 78Q2120 will

assert the COL signal in response to the assertion of TX_EN signal.

Collision test is disabled in PCS bypass mode. Collision test is

enabled regardless of the duplex mode of operation.

RESERVED

MR1 - STATUS REGISTER

Bits 1.15 through 1.11 reflect the ability of the 78Q2120 as configured by the TECH[2:0] pins They do not reflect any

ability changes made via the MII management interface to bits 0.13 (SPEEDSL), 0.12 (ANEGEN) and 0.8 (DUPLEX).

BIT

1.15

1.14

1.13

1.12

1.11

1.10:6

1.5

1.4

1.3

1.2

1.1

1.0

SYMBOL

100T4

100X_F

100X_H

10T_F

10T_H

RSVD

ANEGC

RFAULT

ANEGA

LINK

JAB

EXTD

TYPE

R, 0

R, (1)

R, (1)

R, (1)

R, (1)

R, 0

R, 0

R, 0, RC

R, (1)

R, 0

R, 0, RC

R, 1

DESCRIPTION

100BASE-T4 ABILITY: This bit is permanently held at logic zero to

indicate that the 78Q2120 is not capable of 100BASE-T4.

100BASE-TX FULL DUPLEX ABILITY: (0 = not able, 1 = able)

100BASE-TX HALF DUPLEX ABILITY: (0 = not able, 1 = able)

10BASE-T FULL DUPLEX ABILITY: (0 = not able, 1 = able)

10BASE-T HALF DUPLEX ABILITY: (0 = not able, 1 = able)

RESERVED

AUTO-NEGOTIATION COMPLETE: A logic one indicates a) that

the auto-negotiation process has completed, b) that the contents of

registers MR4, 5, and 6 are valid, and c) that a highest common

denominator rate and mode have been found.

REMOTE FAULT: A logic one indicates that a remote fault condition has

been detected. It remains set until it is cleared. This bit can only be

cleared by reading this register (MR1) via the management interface.

AUTO-NEGOTIATION ABILITY: This bit, when set, indicates the

ability to perform auto-negotiation. The value of this bit is

determined by the ANEGA pin.

LINK STATUS: A logic one indicates that a valid link has been

established. If the link status should transition from an OK status to

a NOT-OK status, this bit will become cleared and remain cleared

until it is read.

JABBER DETECT: In 10Base-T mode, this bit is set during a jabber

event. After a jabber event it remains set until cleared by a read operation.

EXTENDED CAPABILITY: This bit is permanently set to logic one

to indicate that the 78Q2120 provides an extended register set

(MR2 and beyond).

12

Share Link: