SMS44S Ver la hoja de datos (PDF) - Summit Microelectronics
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SMS44S Datasheet PDF : 16 Pages
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SMS44
Input Data Protocol
The protocol defines any device that sends data onto the
bus as a “transmitter” and any device that receives data as
a “receiver.” The device controlling data transmission is
called the “master” and the controlled device is called the
“slave.” In all cases the SMS44 will be a “slave” device,
since it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time, because changes on the data line while SCL is high
will be interpreted as start or stop condition.
Symbol
Parameter
fSCL
t
LOW
tHIGH
tBUF
tSU:STA
tHD:STA
tSU:STO
tAA
tDH
tR
tF
tSU:DAT
tHD:DAT
TI
SCL clock frequency
Clock low period
Clock high period
Bus free time
Start condition setup time
Start condition hold time
Stop condition setup time
Clock edge to valid output
Data Out hold time
SCL and SDA rise time
SCL and SDA fall time
Data In setup time
Data In hold time
Noise filter SCL and SDA
t
Write cycle time
WR
Conditions
Before new transmission
SCL low to valid SDA (cycle n)
SCL low (cycle n+1) to SDA change
Noise suppression
Table 8. Memory Operating Characteristics
tR
tF
tHIGH
tLOW
SCL
Min.
0
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
250
0
Max. Units
100
kHz
µs
µs
µs
µs
µs
µs
3.5
µs
µs
1000
ns
300
ns
ns
ns
100
ns
5
ms
2047 Table08 2.2
tSU:STA
SDA In
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tAA
tDH
SDA Out
SUMMIT MICROELECTRONICS, Inc.
Figure 8. Memory Operating Characteristics
2047 2.3 10/23/00
2047 Fig08 2.1
11
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