CY8C21345(2010) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY8C21345 Datasheet PDF : 35 Pages
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CY8C21345
CY8C22345, CY8C22545
PSoC Functional Overview
The PSoC family consists of many On-Chip Controller devices.
These devices are designed to replace multiple traditional
MCU-based system components with one low cost single-chip
programmable device. PSoC devices include configurable
blocks of analog and digital logic, and programmable
interconnects. This architecture enables the user to create
customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts
and packages.
The PSoC architecture, shown in Figure 1, consists of four main
areas: PSoC Core, Digital System, Analog System, and System
Resources. Configurable global busing allows the combining of
all the device resources into a complete custom system. The
PSoC family can have up to five I/O ports connecting to the
global digital and analog interconnects, providing access to eight
digital blocks and six analog blocks.
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture micro-
processor. The CPU uses an interrupt controller with 21 vectors,
to simplify the programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 16 KB of Flash for program storage, 1K
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator). The 24 MHz
IMO can also be doubled to 48 MHz for use by the digital system.
A low power 32 kHz ILO (internal low speed oscillator) is
provided for the Sleep timer and WDT. If crystal accuracy is
required, the ECO (32.768 kHz external crystal oscillator) is
available for use as a Real Time Clock (RTC), and can optionally
generate a crystal-accurate 24 MHz system clock using a PLL.
The clocks, together with programmable clock dividers (as a
System Resource), provide the flexibility to integrate almost any
timing requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin can also generate a system interrupt on
high level, low level, and change from last read.
Digital System
The Digital System is composed of eight digital PSoC blocks.
Each block is an 8-bit resource that may be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user module references.
Figure 1. Digital System Block Diagram
Port 4
Port 3
Port 2
Port 1
Port 0
8
8
Digital Clocks To System Bus
From Core
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row 0
4
DBC00 DBC01 DCC02 DCC03
4
Row 1
DBC00 DBC01 DCC02 DCC03
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations are:
■ PWMs (8 to 32-Bit)
■ PWMs with Dead band (8 to 32-Bit)
■ Counters (8 to 32-Bit)
■ Timers (8 to 32-Bit)
■ UART 8 Bit with Selectable Parity (Up to Two)
■ SPI Master and Slave (Up to Two)
■ Shift Register (1 to 32-Bit)
■ I2C Slave and Master (One Available as a System Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32-Bit)
■ IrDA (Up to Two)
■ Pseudo Random Sequence Generators (8 to 32-Bit)
The digital blocks may be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides a choice of
system resources for your application. Family resources are
shown in Table 1 on page 5.
Document Number: 001-43084 Rev. *L
Page 3 of 35
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