CY8C21345(2010) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY8C21345 Datasheet PDF : 35 Pages
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CY8C21345
CY8C22345, CY8C22545
Pinouts
This PSoC device family is available in a variety of packages that are listed in the following tables. Every port pin (labeled with a “P”)
is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
CY8C22345, CY8C21345 28-Pin SOIC
Table 2. Pin Definitions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Type
Pin Name
Digital Analog
Description
I/O I, MR P0[7] Integration Capacitor for MR
I/O I, ML P0[5] Integration Capacitor for ML
I/O I, ML P0[3]
I/O I, ML P0[1]
I/O I, ML P2[7] To Compare Column 0
I/O
ML
P2[5] Optional ADC External Vref
I/O
ML
P2[3]
I/O
ML
P2[1]
Power
Vss Ground Connection
I/O
ML
P1[7] I2C Serial Clock (SCL)
I/O
ML
P1[5] I2C Serial Data (SDA)
I/O
ML
P1[3]
I/O
ML
P1[1] I2C Serial Clock (SCL),
ISSP-SCLK[4]
Power
Vss Ground Connection
I/O
MR
P1[0] I2C Serial Clock (SCL),
ISSP-SDATA[4]
I/O
MR
P1[2]
I/O
MR
P1[4] Optional External Clock Input
(EXT-CLK)
I/O
MR
P1[6]
Input
XRES Active High Pin Reset with
Internal Pull Down
I/O
MR
P2[0]
I/O
MR
P2[2]
I/O
MR
P2[4]
I/O I, MR P2[6] To Compare Column 1
I/O I, MR P0[0]
I/O I, MR P0[2]
I/O I, MR P0[4]
I/O I, MR P0[6]
Power
Vdd Supply Voltage
Figure 3. Pin Diagram
AI, MR, P0[7] 1
AI, ML, P0[5] 2
AI, ML, P0[3] 3
AI, ML, P0[1] 4
AI, ML, P2[7] 5
ADC_Ext_Vref, ML, P2[5] 6
ML, P2[3] 7
ML, P2[1] 8
Vss 9
I2C SCL, ML, P1[7] 10
I2C SDA, ML, P1[5] 11
ML, P1[3] 12
I2C SCL, ML, P1[1] 13
Vss 14
28
27
26
25
24
23
SOIC 22
21
20
19
18
17
16
15
Vdd
P0[6], MR, AI
P0[4], MR, AI
P0[2], MR, AI
P0[0], MR, AI
P2[6], MR, AI
P2[4], MR
P2[2], MR
P2[0], MR
XRES
P1[6], MR
P1[4], MR, EXTCLK
P1[2], MR
P1[0], MR, I2C SDATA
LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input.
Note
4. ISSP pin which is not Hi-Z at POR.
Document Number: 001-43084 Rev. *L
Page 9 of 35
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