AD2S1200
tCK
CLKIN
SAMPLE
CS
t1
t2
RD
RDVEL
SO
t1
t3
t3
t5
t4
t6
POS
t5
t4
t6
t7
t7
VEL
RD
SCLK
SO
t8
MSB
t9
t10
MSB–1
tSCLK
t11
LSB
RDVEL DOS
LOT
PAR
Figure 8. Serial Port Read Timing
Table 6. Serial Port Timing
Parameter
Description
t8
MSB Read Time from RD/CS to SCLK
t9
Enable Time RD/CS to DB Valid
t10
Delay SCLK to DB Valid
t11
Disable Time RD/CS to DB High Z
tSCLK
Serial Clock Period (25 MHz Max)
Min
Typ
15 ns
40 ns
Max
tSCLK
12 ns
14 ns
18 ns
Rev. 0 | Page 15 of 24