74ALVT16823 Ver la hoja de datos (PDF) - Nexperia B.V. All rights reserved
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74ALVT16823
Nexperia B.V. All rights reserved
74ALVT16823 Datasheet PDF : 18 Pages
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Nexperia
74ALVT16823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
1D0, 1D1, 1D2, 1D3, 1D4,
1D5, 1D6, 1D7, 1D8
1Q0, 1Q1, 1Q2, 1Q3, 1Q4,
1Q5, 1Q6, 1Q7, 1Q8
2D0, 2D1, 2D2, 2D3, 2D4,
2D5, 2D6, 2D7, 2D8
2Q0, 2Q1, 2Q2, 2Q3, 2Q4,
2Q5, 2Q6, 2Q7, 2Q8
1MR, 2MR
1OE, 2OE
1CP, 2CP
1CE, 2CE
GND
VCC
Pin
54, 52, 51, 49, 48,
47, 45, 44, 43
3, 5, 6, 8, 9,
10, 12, 13, 14
42, 41, 40, 38, 37,
36, 34, 33, 31
15, 16, 17, 19, 20,
21, 23, 24, 26
1, 28
2, 27
56, 29
55, 30
4, 11, 18, 25,
32, 39, 46, 53
7, 22, 35, 50
Description
data inputs
data outputs
data inputs
data outputs
master reset input (active-LOW)
output enable inputs (active LOW)
clock pulse inputs (active rising edge)
clock enable input (active-LOW)
ground (0 V)
supply voltage
6 Functional description
Table 3. Function table [1]
Operating mode
Input
nOE
clear
L
load and read data
L
nMR
L
H
nCE
X
L
hold
L
H
H
high-impedance
H
X
X
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition;
↑ = not a LOW-to-HIGH clock transition.
nCP
X
↑
↑
X
nDn
X
h
l
X
X
Output
nQn
L
H
L
NC
Z
74ALVT16823
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 22 January 2018
© Nexperia B.V. 2018. All rights reserved.
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