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GS71024GT-10

64K x 24 1.5Mb Asynchronous SRAM

Giga Semiconductor 

GS71024T/U

Write Cycle

Parameter

Write cycle time

Address valid to end of write

Chip enable to end of write (CE1, CE2)

MUX control to end of write (V/S)

Data set up time

Data hold time

Write pulse width

Address set up time

MUX control set up time

Write recovery time (WE)

Write recovery time (V/S, CE1, CE2 )

Output Low Z from end of write

Write to output in High Z

-8

-9

-10

-12

-15

Symbol

Unit

Min Max Min Max Min Max Min Max Min Max

tWC

8 — 9 — 10 — 12 — 15 — ns

tAW 5.5 — 6.25 — 7 — 8 — 10 — ns

tCW 5.5 — 6.25 — 7 — 8 — 10 — ns

tVW 5.5 — 6.25 — 7 — 8 — 10 — ns

tDW

4 — 4.5 — 5 — 6 — 7 — ns

tDH

0 — 0 — 0 — 0 — 0 — ns

tWP 5.5 — 6.25 — 7 — 8 — 10 — ns

tAS

0 — 0 — 0 — 0 — 0 — ns

tVS

0 — 0 — 0 — 0 — 0 — ns

tWR

0 — 0 — 0 — 0 — 0 — ns

tWR1

0 — 0 — 0 — 0 — 0 — ns

tWLZ*

2 — 2.5 —

3

—3

—

3

— ns

tWHZ* — 4 — 4.5 — 5 — 6 — 7 ns

* These parameters are sampled and are not 100% tested

Rev: 1.05 11/2004

8/13

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 1999, GSI Technology

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