GS71024GT-10 Ver la hoja de datos (PDF) - Giga Semiconductor

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GS71024GT-10

64K x 24 1.5Mb Asynchronous SRAM

Giga Semiconductor 

GS71024T/U

Write Cycle 1: WE control

tWC

Address

tAW

tWR

OE

tCW

CE1(*1)

V/S

tVS

tVW

tAS

tWP (*2)

WE

Data In

tDW

tDH

Data valid

tWHZ

tWLZ

Data Out

High impedance

(*3)

(*3)

*1 CE1 represents both CE1 low and CE2 high.

*2 Write is executed when both CE1 and WE are at low simultaneously.

*3 Do not apply the data input voltage to the output while DQ pin is in output condition.

Address

OE

CE1(*1)

V/S

WE

Data In

Write Cycle 2: CE control

tWC

tAW

tWR1

tAS

tCW

tVW

tWP

tDW

tDH

Data valid

Data Out

High impedance

*1 CE1 represents both CE1 low and CE2 high.

Rev: 1.05 11/2004

9/13

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 1999, GSI Technology

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