ML2721 Ver la hoja de datos (PDF) - Micro Linear Corporation

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ML2721

Low IF Digital Cordless Transceiver

Micro Linear Corporation 

PRELIMINARY

CONTROL INTERFACES AND REGISTER DESCRIPTION (continued)

ML2721

RES (Reserved) All 4 Registers

These bits are reserved. Clear these bits to 0 (zero) for

normal operation. When power is reset all of the registers’

data fields are cleared to 0 (zero).

RD0 Register #0 Only

Reference Divide Bit Zero. This bit sets the reference

division of the PLL to either 6 or 12. See Table 15.

LOL LO Shift for Transmit LO Shift for Receive

0

0

+1.024MHz

1

+1.024MHz

0

REGISTER CONFIGURATIONS AT POWER UP (DEFAULT)

All register values are cleared to 0 (zero). Power up is

defined as occurring when VDD³2.0V.

The register default values are valid 1ns after power up.

Table 15. Reference Frequency Select

RXCL Register #0 Only

Receive Closed Loop Bit. This bit is used in Receive mode

to put the PLL into either open loop or closed loop. See

Table 16.

RXCL

0

1

Receive PLL Mode

PLL open loop

PLL closed loop

Table 16. PLL Mode in Normal Receive Operation

TMODE Register #2 Only

This bit is used to activate the automatic filter alignment

circuitry. For normal operations this bit must be cleared to

0 (zero).

QPP Register #0 Only

This bit sets the charge pump polarity to sink or source

current. For a majority of applications this bit is cleared

(QPP = 0). For applications where an external amplifier is

in the loop filter the bit is set to 1 to change the charge

pump polarity. See Table 17.

QPP

PLL Charge Pump Polarity

0

Frequency signal > frequency reference.

Charge pump sinks current.

1

Frequency signal > frequency reference.

Charge pump sources current.

Table 17. PLL Charge Pump Polarity

January, 2000 PRELIMINARY DATASHEET

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