Q67100-H6440 Ver la hoja de datos (PDF) - Siemens AG
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Q67100-H6440 Datasheet PDF : 253 Pages
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SAB 82538
SAF 82538
q Statistical multiplexing
q Continuous transmission of 1 to 32 bytes possible
q Programmable Preamble (8 bit) with selectable repetition rate
(HDLC/SDLC and BISYNC)
q Data rate up to 10 Mbit/s
q Master clock mode with data rate up to 4 Mbit/s
Protocol Support (HDLC / SDLC)
q Various types of protocol support depending on operating mode
– Auto mode (automatic handling of S and I frames)
– Non-auto mode
– Transparent mode
q Handling of bit oriented functions
q Support of LAPB / LAPD / SDLC / HDLC protocol in auto mode
(I- and S-frame handling)
q Modulo 8 or modulo 128 operation
q Programmable time-out and retry conditions
q Programmable maximum packet size checking
MP Interface and Ports
q 64 byte FIFOs per channel and direction (byte or word access)
q 8/16 bit microprocessor bus interface (Intel or Motorola type)
q All registers directly accessible (byte and word access)
q Efficient transfer of data blocks from/to system memory via DMA or interrupt request
q Support of Daisy Chaining and Slave Operation with Interrupt Vector generation
q 28-bit programmable universal I/Os
General
q Advanced CMOS technology
q Low power consumption: active 200 mW at 2 MHz/standby 20 mW (typical values)
q P-MQFP-160 Package
Semiconductor Group
9
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