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BR34L02-W

2Kbit Serial I2C BUS EEPROM For SPD DRAM Memory Module

ROHM Semiconductor 

●Data transfer on the I2C-bus

○Data transfer on the I2C-bus

The bus considered to be busy after the START condition, and be free again a certain time after the STOP condition.

Every byte put on the SDA line must be 8-bits long, and after each byte, the signal of a acknowledge is obligatory.

The devices have the master and slave. The master is the device which initiates and ends a data transfer on the bus and

generates the clock signals to permit that transfer.

The slave is the device which controlled with the unique address. EEPROM is slave. Also the device transmitting during

transferring the data is called transmitter, and the device received is called receiver.

○START CONDITION (RECOGNITION OF START BIT)

・All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH.

・The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command

until this condition has been met. （See Fig.1-(b) START/STOP BIT TIMING）

○STOP CONDITION (RECOGNITION OF STOP BIT)

・All commands must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH.

（See Fig.1-(b) START/STOP BIT TIMING）

○ACKNOWLEDGE

・Acknowledge is a software convention used to indicate successful data transfers. The transmitter device will release the

bus after transmitting eight bits. (When inputting the slave address in the write or read operation, transmitter is

μ-COM. When outputting the data in the read operation, it is this device.)

・During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that the eight bits of data has been

received. (When inputting the slave address in the write or read operation, receiver is this device. When outputting the

data in the read operation, it is μ-COM.)

・The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit).

・In the WRITE mode, the device will respond with an Acknowledge, after the receipt of each subsequent 8-bit word

(word address and write data).

・In the READ mode, the device will transmit eight bit of data, release the SDA line, and monitor the line for an

Acknowledge.

・If an Acknowledge is detected, and no STOP condition is generated by the master, the device will continue to transmit

the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP

condition before returning to the standby mode.

○DEVICE ADDRESSING

・Following a START condition, the master output the slave address to be accessed. The most significant four bits

of the slave address are the “device type indentifier,” for the device this is fixed as “1010.” (In access to WP register,

this code use "0110".)

・The next three bit (device address) identify the specified device on the bus. The device address is defined by the state of

A0,A1 and A2 input pins. This IC works only when the device address inputted from SDA pin correspond to the state of

A0,A1 and A2 input pins. Using this address scheme, up to eight devices may be connected to the bus. The last bit of

the stream (R/W…READ/WRITE) determines the operation to be performed.

R/W=0

R/W=1

WRITE (including word address input of Random Read)

READ

Device Type

1010

0110

Device Address

A2 A1

A0

R/W

A2 A1

A0

R/W

Access to Memory

Access to Write Protect Register

7/16

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