49LF002B Ver la hoja de datos (PDF) - Silicon Storage Technology
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49LF002B Datasheet PDF : 43 Pages
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2 Mbit / 3 Mbit / 4 Mbit LPC Firmware Flash
SST49LF002B / SST49LF003B / SST49LF004B
Data Sheet
Clock
The LCLK pin accepts a clock input from the host controller.
stable before the start of a GPI register Read and remain
stable until the Read cycle is complete. The pins must be
driven low, VIL, or high, VIH but not left unconnected (float).
Input/Output Communications
The LAD[3:0] pins are used to serially communicate cycle
information such as cycle type, cycle direction, ID selection,
address, data, and sync fields.
Input Communication Frame
The LFRAME# pin is used to indicate start of a LPC bus
cycle. The pin is also used to abort an LPC bus cycle in
progress.
Interface Mode Select
The MODE pin is used to set the interface mode. If the
mode pin is set to logic high, the device is in PP mode. If
the mode pin is set low, the device is in the LPC mode. The
mode selection pin must be configured prior to device oper-
ation. The mode pin is internally pulled down if the pin is left
unconnected.
Reset
A VIL on INIT# or RST# pin initiates a device reset. INIT#
and RST# pins have the same function internally. It is
required to drive INIT# or RST# pins low during a system
reset to ensure proper CPU initialization. During a Read
operation, driving INIT# or RST# pins low deselects the
device and places the output drivers, LAD[3:0], in a high
impedance state. The reset signal must be held low for a
minimum of time TRSTP. A reset latency occurs if a reset pro-
cedure is performed during a Program or Erase operation.
See Table 28 and Table 29, Reset Timing Parameters, for
more information. A device reset during an active Program
or Erase operation will abort the operation and memory
contents may become invalid due to data being altered or
corrupted from an incomplete Erase or Program operation.
Identification Inputs
These pins are part of a mechanism that allows multiple
devices to be attached to the same bus. The strapping of
these pins is used to identify the component. The boot
device must have ID[3:0] = 0; all subsequent devices
should use sequential count-up strapping. These pins are
internally pulled-down with a resistor between 20-100 KΩ.
Write Protect / Top Block Lock
The Top Boot Lock (TBL#) and Write Protect (WP#) pins
are provided for hardware write protection of device mem-
ory in the SST49LF00xB. The TBL# pin is used to write pro-
tect 16 boot sectors (64 KByte) at the highest memory
address range for the SST49LF003B/004B and 4 boot sec-
tors (16 KByte) for the SST49LF002B. The WP# pin write
protects the remaining sectors in the flash memory.
An active low signal at the TBL# pin prevents Program and
Erase operations of the top boot block. When TBL# pin is
held high, the hardware write protection of the top boot
block is disabled. The WP# pin serves the same function for
the remaining blocks of the device memory. The TBL# and
WP# pins write protection functions operate independently
of one another. Both TBL# and WP# pins must be set to
their required protection states prior to starting a Program or
Erase operation. A logic level change occurring at the TBL#
or WP# pin during a Program or Erase operation could
cause unpredictable results.
Row / Column Select
The R/C# pin is used to control the multiplex address
inputs in Parallel Programming (PP) mode. The column
addresses are mapped to the higher internal addresses
(AMS-11) shown in Table 2, and the row addresses are
mapped to the lower internal addresses (A10-0).
TABLE 2: MOST SIGNIFICANT ADDRESSES
AMS Device
A17 SST49LF002B
A18 SST49LF003B / SST49LF004B
T2.0 1232
Output Enable
The OE# pin is used to gate the output data buffers in PP
mode.
Write Enable
The WE# pin is used to control the write operations in PP
mode.
General Purpose Inputs
The General Purpose Inputs (GPI[4:0]) can be used as dig-
ital inputs for the CPU to read. The GPI register holds the
values on these pins. The data on the GPI pins must be
No Connection
These pins are not connected internally.
©2005 Silicon Storage Technology, Inc.
9
S71232-05-000
1/05
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