UP6204 Ver la hoja de datos (PDF) - Unspecified

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UP6204

Compact Three-Phase Synchronous-Rectified Buck Controller

Unspecified 

Preliminary

uP6204

connected to SS pin after a 800us delay time TDLY at T1.

The non-inverting input of the error amplifier VEAP is equal

to V and ramp up linearly to V . (Neglect the voltage

SS

REF

drop caused by droop setting resistor RDRP, see the related

section for details.) Consequently, the FB voltage VFB is

regulated to VEAP and ramp up linearly to VREF.

VR2 is default selected as VREF during soft start cycle

regardless of the status of VID0 and VID1. The output

voltage reaches power on default output voltage defined by

R2 pin at T2 and stays there for a time interval TDFT.

Functional Description

Table 4. Typical Power On Periods with CSS = 4.7nF

Parameter

Symbol

Nominal Adjustable

Value Range

Start Delay Time

Soft Start Time

Enable to Output

in Regulation

PWR ON Default

Voltage Period

TDLY

TSS

TRAMP =

TDLY + TSS

200us

3ms

3.2ms

NA

1~4ms

1.2~4.2ms

TDFT

200ms

NA

SS

RDRP

EAP

FB

VREF

Maximum

Current =

160uA

Error

Amplifier

ISEN

Operation Frequency Programming

A resistor RRT connected to RT pin programs the oscillation

frequency as:

fOSC

=

10000

RRT (kΩ)

(kHz)

Figure 6 shows the relationship between oscillation

frequency and RRT.

COMP

uP6204

1000

Figure 4. Voltage Control Loop

The uP6204 enters PVID mode (parallel VID mode) and

moves the output voltage to its final level selected by

100

VID[1:0] and voltages at R1/R2/R3/R4 after T3. The output

voltage transition slew rate is identical to the slew rate

during TSS. Table 4 shows typical time period of soft start

cycle of uP6204.

Controller Enable and

Power On Rest

SS

TRAMP

PWR ON Default

Output Voltage = VR2

VOUT

Output Voltage

Selected by VID[0:1]

T0 T1

TDLY

T2

T3

Time

TSS

TDFT

PVID Mode

Figure 5. Power On Sequence

10

10

100

RRT (kohm)

1000

Figure 6. Switching Frequency vs. RRT.

Channel Current Sensing and Current Balance

The uP6204 senses the phase currents for current balance

by sensing the voltage across the lower switches when

they turn on as shown in Figure 7. The sampled-and-held

current is calculated as:

ISEN [1 :

3]

=

10mV − VPHASE [1:

RSEN[1: 3]

3]

uPI Semiconductor Corp., http://www.upi-semi.com

9

Rev. P01, File Name: uP6204-DS-P01000

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