LTC6820 Ver la hoja de datos (PDF) - Linear Technology
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LTC6820 Datasheet PDF : 28 Pages
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Block Diagram
VDD
0.1µF
VDD
MSTR
SLOW
POL
PHA
VDDS
RPU
(TO MOSI IF MSTR = 0)
(TO MISO IF MSTR = 1)
VDDS
EN
MOSI
MISO
SCK
CS
GND
LTC6820
EN
CS
READY
IDLE TIMEOUT
WAKE DETECT
2V
VDD
VICMP
3
+
167mV
+–
OPEN
WHEN
IDLE
35k
35k
IBIAS
ICMP
Rx = +1
THRESHOLD
0.5x
Rx = –1
IB
RB1
RBIAS = RB1 + RB2
RB2
Tx = +1
IDRV
Tx = –1
Tx • 20 • IB
IP
RM
IM
6820 BD
Operation
The LTC6820 creates a bidirectional isolated serial port
interface (isoSPI) over a single twisted pair of wires, with
increased safety and noise immunity over a nonisolated
interface. Using transformers, the LTC6820 translates
standard SPI signals (CS, SCK, MOSI and MISO) into pulses
that can be sent back and forth on twisted-pair cables.
A typical system uses two LTC6820 devices. The first is
paired with a microcontroller or other SPI master. Its IP
and IM transmitter/receiver pins are connected across an
isolation barrier to a second LTC6820 that reproduces the
SPI signals for use by one or more slave devices.
The transmitter is a current-regulated differential driver.
The voltage amplitude is determined by the drive current
and the equivalent resistive load (cable characteristic
impedance and termination resistor, RM).
The receiver consists of a window comparator with a
differential voltage threshold, VTCMP. When VIP – VIM
is greater than +VTCMP, the comparator detects a logic
+1. When VIP – VIM is less than –VTCMP, the comparator
detects a logic –1. A logic 0 (null) indicates VIP – VIM is
between the positive and negative thresholds.
The comparator outputs are sent to pulse timers (filters)
that discriminate between short and long pulses.
Selecting Bias Resistors
The adjustable signal amplitude allows the system to trade
power consumption for communication robustness, and
the adjustable comparator threshold allows the system to
account for signal losses.
6820f
9
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