RTL8100 Ver la hoja de datos (PDF) - Realtek Semiconductor
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RTL8100 Datasheet PDF : 58 Pages
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RTL8100B(L)
5.7 Transmit Configuration Register
(Offset 0040h-0043h, R/W)
This register defines the Transmit Configuration for the RTL8100B(L). It controls such functions as Loopback, programmable
Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size.
Bit
31
30-26
25-24
23-22
21-19
18, 17
16
15-11
10-8
R/W
-
R
R/W
R
-
R/W
R/W
-
R/W
Symbol
-
HWVERID_A
IFG1, 0
HWVERID_B
-
LBK1, LBK0
CRC
-
MXDMA2, 1, 0
Description
Reserved
Hardware Version ID A:
Bit30 Bit29 Bit28 Bit27 Bit26 Bit23 Bit22
RTL8139
1
1
0
0
0
0
0
RTL8139A 1 1 1 0 0 0 0
RTL8139A-G 1 1 1 0 1 0 0
RTL8139B 1 1 1 1 0 0 0
RTL8130
1
1
1
1
0
0
0
RTL8139C 1 1 1 0 1 0 0
RTL8100
1
1
1
1
0
1
0
RTL8100B/ 1 1 1 0 1 0 1
8139D
RTL8139C+ 1 1 1 0 1 1 0
RTL8101
1
1
1
0
1
1
1
Reserved
Other combination
Interframe Gap Time: This field allows the user to adjust the
interframe gap time below the standard: 9.6 µs for 10Mbps, 960 ns for
100Mbps. The time can be programmed from 9.6 µs to 8.4 µs (10Mbps)
and 960ns to 840ns (100Mbps). Note that any value other than (1, 1)
will violate the IEEE 802.3 standard.
The formula for the inter frame gap is:
10 Mbps
8.4µs + 0.4(IFG(1:0)) µs
100 Mbps
840ns + 40(IFG(1:0)) ns
Hardware Version ID B
Reserved
Loopback test: There will be no packet on the TX+/- lines under the
Loopback test condition. The loopback function must be independent of
the link state.
00 : normal operation
01 : Reserved
10 : Reserved
11 : Loopback mode
Append CRC: Setting to 1 means that there is no CRC appended at the
end of a packet. Setting to 0 means that there is CRC appended at the
end of a packet.
Reserved
Max DMA Burst Size per Tx DMA Burst: This field sets the
maximum size of transmit DMA data bursts according to the following
table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = 2048 bytes
2001-11-9
16
Rev.1.41
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