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RTL8101

REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER AND MC’97 CONTROLLER WITH POWER MANAGEMENT

Realtek Semiconductor 

15

R

14

R

13

R/W

12-0

R/W

TOK

TUN

OWN

SIZE

RTL8101L

These fields count from 000001 to 111111 in unit of 32 bytes.

This threshold must avoid exceeding 2K bytes.

Transmit OK: Set to 1 indicates that the transmission of a packet was

completed successfully and no transmit underrun has occurred.

Transmit FIFO Underrun: Set to 1 if the Tx FIFO was exhausted

during the transmission of a packet. The RTL8101L can re-transfer data

if the Tx FIFO underruns and can also transmit the packet to the wire

successfully even though the Tx FIFO underruns. That is, when

TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1).

OWN: The RTL8101L sets this bit to 1 when the Tx DMA operation of

this descriptor was completed. The driver must set this bit to 0 when the

Transmit Byte Count (bits 0-12) is written. The default value is 1.

Descriptor Size: The total size in bytes of the data in this descriptor. If

the packet length is more than 1792 byte (0700h), the Tx queue will be

invalid, i.e. the next descriptor will be written only after the OWN bit of

that long packet's descriptor has been set.

5.3 ERSR: Early Rx Status Register

(Offset 0036h, R)

Bit

R/W

7-4

-

3

R

2

R

1

R

Symbol

-

ERGood

ERBad

EROVW

0

R

EROK

Description

Reserved

Early Rx Good packet: This bit is set whenever a packet is completely

received and the packet is good. Writing a 1 to this bit will clear it.

Early Rx Bad packet: This bit is set whenever a packet is completely

received and the packet is bad. Writing a 1 to this bit will clear it.

Early Rx OverWrite: This bit is set when the RTL8101L's local

address pointer is equal to CAPR. In the early mode, this is different

from buffer overflow. It happens that the RTL8101L detected an Rx

error and wanted to fill another packet data from the beginning address

of that error packet. Writing a 1 to this bit will clear it.

Early Rx OK: The power-on value is 0. It is set when the Rx byte count

of the arriving packet exceeds the Rx threshold. After the whole packet is

received, the RTL8101L will set ROK or RER in ISR and clear this bit

simultaneously. Setting this bit will invoke a ROK interrupt.

5.4 Command Register

(Offset 0037h, R/W)

This register is used for issuing commands to the RTL8101L. These commands are issued by setting the corresponding bits for the

function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here.

Bit

R/W

Symbol

Description

7-5

-

-

Reserved

4

R/W

RST

Reset: Setting to 1 forces the RTL8101L to a software reset state which

disables the transmitter and receiver, reinitializes the FIFOs, resets the

system buffer pointer to the initial value (Tx buffer is at TSAD0, Rx

buffer is empty). The values of IDR0-5 and MAR0-7 and PCI

configuration space will have no changes. This bit is 1 during the reset

operation, and is cleared to 0 by the RTL8101L when the reset operation

is complete.

2003-05-28

14

Rev.1.3

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