RTL8208BF Ver la hoja de datos (PDF) - Realtek Semiconductor
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RTL8208BF Datasheet PDF : 65 Pages
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RTL8208B-LF/RTL8208BF-LF
Datasheet
6.1. Register0: Control
Reg. bit
0.15
0.14
Name
Reset
Loopback
0.13 Spd_Sel
Table 11. Register0: Control
Description
1: PHY reset. This bit is self-clearing.
This will loopback TXD to RXD and ignore all activity on
the cable media.
1: Enable loopback
0: Normal operation
When NWay is enabled, this bit reflects the auto negotiation
result (Read Only).
Type
RW/SC
RW
RW
When NWay is disabled, this bit can be set by SMI*.
(Read/Write).
When 100FX is enabled, this bit =1 (Read Only).
0.12 Auto Negotiation
Enable
0.11 Power Down
0.10 Isolate
0.9 Restart Auto
Negotiation
0.8 Duplex Mode
1: 100Mbps
0: 10Mbps
This bit can be set through SMI (Read/Write).
When 100FX is enabled, this bit =0 (Read only).
1: Enable auto negotiation process
0: Disable auto negotiation process
1: Power down. All functions will be disabled except SMI
read/write function
0: Normal operation
1: Electrically isolate the PHY from RMII/SMII/SS-SMII.
PHY is still able to respond to MDC/MDIO
0: Normal operation
1: Restart Auto-Negotiation process
0: Normal operation
When NWay is enabled, this bit reflects the result of auto
negotiation (Read Only).
RW
RW
RW
RW/SC
RW
When NWay is disabled, this bit can be set by SMI*
(Read/Write).
When 100FX is enabled, this bit is determined by the
FX_DUPLEX pin (Read/Write).
1: Full duplex operation
0: Half duplex operation
0.[7:0] Reserved
RO
*SMI: Serial Management Interface composed of MDC, MDIO, that allows the MAC to manage the PHY.
Default
0
0
0
1
(0 for
100FX)
0
0
0
0
0
Reset – In order to reset the RTL8208B(F)-LF using software control, a ‘1’ must be written to bit 15
using an SMI write operation. The bit clears itself after the reset process has completed. Writes to other
Control register bits will have no effect until the reset process has completed (approximately 1µs).
Writing a ‘0’ to this bit has no effect. Because this bit is self-clearing after a few cycles from a write
operation, it will return a ‘0’ when read.
Single-Chip Octal 10/100-TX/FX PHY Transceiver
14
Track ID: JATR-1076-21 Rev. 1.3
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