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BD9486F

1ch Boost up type White LED Driver for large LCD

ROHM Semiconductor 

BD9486F

Datasheet

●3.2.7 OVP Setting

The OVP terminal is the input for over-voltage protection of output voltage.

The OVP pin is high impedance, because the internal resistance is not connected to a certain bias.

Detection voltage of VOUT is set by dividing resistors R1 and R2. The resistor values can be calculated by the formula

below.

○OVP detection equation

If VOUT is boosted abnormally, VOVPDET, the detect

voltage of OVP, R1, R2 can be expressed by the following formula.

R1  R2[k]  (VOVPDET[V]  3.0[V]) [k]

3.0[V]

○OVP release equation

By using R1 and R2 in the above equation, the release voltage of

OVP, VOVPCAN can be expressed as follows.

VOVPCAN



2.8V



(R1[k]  R2[k])

R2[k]

[V]

Figure 27. OVP setting example

【setting example】

If the normal output voltage, VOUT is 40V, the detect voltage of OVP is 48V, R2 is 10k ohm, R1 is calculated as follows.

R1  R2[k]  (VOVPDET[V]  3.0[V])  10[k]  (48[V]  3[V])  150　[k]

3.0[V]

3[V]

By using these R1 and R2, the release voltage of OVP, VOVPCAN can be calculated as follows.

VOVPCAN



2.8[V] 

(R1[k]  R2[k])

R2[k]



2.8[V] 

10[k] 150[k]

10[k]

[V]　

44.8　[V]

●3.2.8 Interval Until Latch Off Setting

About over boost protection (FBMAX), the capacitance value of CP terminal can set the time of latch-off. About the

behavior from abnormal detection to latch-off, please refer to the section “3.5.6 Timing Chart”.

The condition FB>4.0V(typ.) and PWM=H continues more than four GATE clocks, the CP terminal charge is started by

3μA. After that, only the FB voltage is monitored. As the CP voltage reaches to 3.0V(typ.), IC will be latched off.

The time LATCHTIME to reach to latch-off is set by CP terminal capacitance as follows.

LATCHTIME



CCP[F]　 3.0　[V]

3.0　[A]

　[sec]

【setting example】

If the capacitor of CP pin is 0.47μF, the timer latch interval is as follows.

LATCHTIME



0.47　[F]　 3.0　[V]

3.0　[A]

　 470　[msec]

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