LPC47N237-MD Ver la hoja de datos (PDF) - SMSC -> Microchip
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LPC47N237-MD Datasheet PDF : 138 Pages
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3.3v I/O Controller for Port Replicators and Docking Stations
10.1 UART Power Management ............................................................................................................ 66
10.1.1 Exit Auto Powerdown ..........................................................................................................................66
10.2 Parallel Port Power Management .................................................................................................. 66
10.2.1 Exit Auto Powerdown ..........................................................................................................................67
Chapter 11 Serial IRQ........................................................................................................................ 68
11.1 Timing Diagrams For SER_IRQ Cycle .......................................................................................... 68
11.1.1 SER_IRQ Cycle Control ......................................................................................................................69
11.1.2 SER_IRQ Data Frame ........................................................................................................................69
11.1.3 Stop Cycle Control ..............................................................................................................................70
11.1.4 Latency................................................................................................................................................70
11.1.5 EOI/ISR Read Latency........................................................................................................................70
11.1.6 AC/DC Specification Issue ..................................................................................................................70
11.1.7 Reset and Initialization ........................................................................................................................71
Chapter 12 PCI CLKRUN Support .................................................................................................. 72
12.1 Overview ........................................................................................................................................ 72
12.2 nCLKRUN for Serial IRQ ............................................................................................................... 72
12.3 nCLKRUN for nLDRQ .................................................................................................................... 72
12.4 Using nCLKRUN ............................................................................................................................ 72
Chapter 13 LPC General Purpose I/O .............................................................................................. 75
13.1 Description ..................................................................................................................................... 75
13.2 GPIO Control.................................................................................................................................. 75
13.3 GPIO Operation ............................................................................................................................. 76
Chapter 14 PME Support................................................................................................................... 78
Chapter 15 SMBus GPIO Block ........................................................................................................ 79
15.1 SMBus Slave Controller................................................................................................................. 79
15.1.1 SMBus Pins.........................................................................................................................................79
15.1.2 Bus Protocols ......................................................................................................................................80
Write Byte..........................................................................................................................................................80
Read Byte..........................................................................................................................................................80
15.1.3 Slave Address .....................................................................................................................................80
15.1.4 Invalid Protocol Response Behavior....................................................................................................81
15.1.5 General Call Address Response .........................................................................................................81
15.1.6 Slave Device Time-Out .......................................................................................................................81
15.1.7 Stretching the SCLK Signal.................................................................................................................81
15.1.8 SMBus Timing.....................................................................................................................................81
15.1.9 Bus Reset Sequence ..........................................................................................................................81
15.1.10 SMBus Alert Response .......................................................................................................................82
15.2 SMBus Isolation Logic ................................................................................................................... 82
15.3 SMBus Controlled GPIOs .............................................................................................................. 83
15.3.1 GPIO Pins ...........................................................................................................................................84
15.4 SMBus GPIO Registers ................................................................................................................. 84
15.4.1 Direction Registers..............................................................................................................................84
15.4.2 Output Type Registers ........................................................................................................................84
15.4.3 Data Registers ....................................................................................................................................84
15.4.4 GPIO Mask Registers .........................................................................................................................84
15.4.5 GPIO Change Status Register ............................................................................................................85
15.5 Operation of SMBus Interrupt ........................................................................................................ 85
Chapter 16 Runtime Registers........................................................................................................... 89
16.1 Runtime Registers Block Summary ............................................................................................... 89
16.2 Runtime Registers Block Description ............................................................................................ 89
Chapter 17 Configuration .................................................................................................................. 91
17.1 Configuration Access Ports............................................................................................................ 91
SMSC DS – LPC47N237
Page 5
DATASHEET
Revision 0.3 (10-26-04)
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