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LPC47N237-MD

3.3v I/O Controller for Port Replicators and Docking Stations

SMSC -> Microchip 

3.3v I/O Controller for Port Replicators and Docking Stations

Table 8.1 - Addressing the Serial Port .........................................................................................................................29

Table 8.2 – UART Interrupt Control Table .....................................................................................................................32

Table 8.3 – UART Baud Rates.....................................................................................................................................39

Table 8.4 – UART Reset Function Table.......................................................................................................................40

Table 8.5 – Register Summary for an Individual UART Channel .................................................................................41

Table 9.1 - Parallel Port Connector ...............................................................................................................................45

Table 9.2 - EPP Pin Descriptions ..................................................................................................................................51

Table 9.3 - ECP Pin Descriptions..................................................................................................................................53

Table 9.4 - ECP Register Definitions .............................................................................................................................54

Table 9.5 – Parallel Port Mode Description....................................................................................................................55

Table 9.6 - Extended Control Register ..........................................................................................................................60

Table 9.7 - Parallel Port IRQ Selection ........................................................................................................................60

Table 9.8 - Parallel Port DMA Selection .......................................................................................................................60

Table 9.9 – ECP Forward/Reserve Channel Commands...............................................................................................62

Table 11.1 - SER_IRQ Sampling Periods ....................................................................................................................69

Table 12.1 – LPC47N237 nCLKRUN Function ............................................................................................................73

Table 13.1 – General Purpose I/O Port Assignments ..................................................................................................75

Table 13.2 - GPIO Configuration Summary..................................................................................................................76

Table 13.3 – GPIO Read/Write Behavior .....................................................................................................................77

Table 15.1 – SMBus Pins.............................................................................................................................................80

Table 15.2 − SMBus Write Byte Protocol .....................................................................................................................80

Table 15.3 − SMBus Read Byte Protocol .....................................................................................................................80

Table 15.4 – SMBus GPIO Pins...................................................................................................................................84

Table 15.5 – SMBus GPIO Events State Table in LPC47N237 ...................................................................................86

Table 16.1 - Runtime Register Block Summary ...........................................................................................................89

Table 16.2 – Runtime Registers Block Description ......................................................................................................89

Table 17.1 – Configuration Access Ports .....................................................................................................................91

Table 17.2 – Configuration Registers Summary...........................................................................................................93

Table 17.3 – CR00 .......................................................................................................................................................95

Table 17.4 – CR01 .......................................................................................................................................................96

Table 17.5 – CR02 .......................................................................................................................................................96

Table 17.6 – CR04 .......................................................................................................................................................97

Table 17.7 – CR07 .......................................................................................................................................................98

Table 17.8 – CR09 .......................................................................................................................................................98

Table 17.9 – CR0A.......................................................................................................................................................99

Table 17.10 – CR0C ....................................................................................................................................................99

Table 17.11 – CR0F...................................................................................................................................................100

Table 17.12 – CR10 ...................................................................................................................................................100

Table 17.13 – CR11 ...................................................................................................................................................101

Table 17.14 – CR12 ...................................................................................................................................................101

Table 17.15 – CR13 ...................................................................................................................................................102

Table 17.16 - CR15....................................................................................................................................................102

Table 17.17 – CR21 ...................................................................................................................................................103

Table 17.18 - CR22....................................................................................................................................................103

Table 17.19 - CR23....................................................................................................................................................104

Table 17.20 - Parallel Port Addressing Options .........................................................................................................104

Table 17.21 - CR24....................................................................................................................................................104

Table 17.22 - CR26....................................................................................................................................................105

Table 17.23 - DMA Selection .....................................................................................................................................105

Table 17.24 - CR27....................................................................................................................................................105

Table 17.25 – IRQ Encoding ......................................................................................................................................106

Table 17.26 – CR28 ...................................................................................................................................................106

Table 17.27 – UART Interrupt Operation ...................................................................................................................107

Table 17.28 – CR29 ...................................................................................................................................................107

Table 17.29 – CR2F...................................................................................................................................................108

Table 17.30 – CR30 ...................................................................................................................................................108

Table 17.31 – CR37 ...................................................................................................................................................109

Table 17.32 – CR38 ...................................................................................................................................................109

Table 17.33 – CR39 ...................................................................................................................................................110

Table 17.34 – I/O Base Address Configuration Register Description .........................................................................110

Revision 0.3 (10-26-04)

Page 8

DATASHEET

SMSC DS – LPC47N237

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