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74VCX32373

Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary)

Fairchild Semiconductor 

AC Loading and Waveforms

Preliminary

TEST

tPLH, tPHL

tPZL, tPLZ

tPZH, tPHZ

SWITCH

Open

6V at VCC = 3.3 ± 0.3V;

VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V

GND

FIGURE 1. AC Test Circuit

FIGURE 2. Waveform for Inverting and

Non-Inverting Functions

FIGURE 3. 3-STATE Output HIGH Enable and

Disable Times for Low Voltage Logic

FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic

FIGURE 5. Propagation Delay, Pulse Width and

trec Waveforms

Symbol

Vmi

Vmo

VX

VY

3.3V ± 0.3V

1.5V

1.5V

VOL +0.3V

VOH −0.3V

FIGURE 6. Setup Time, Hold Time and

Recovery Time for Low Voltage Logic

VCC

2.5V ± 0.2V

VCC/2

VCC/2

VOL +0.15V

VOH −0.15V

1.8V ± 0.15V

VCC/2

VCC/2

VOL +0.15V

VOH −0.15V

7

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