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FM1608B Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza
componentes Descripción
Lista de partido
FM1608B
Cypress
Cypress Semiconductor Cypress
FM1608B Datasheet PDF : 18 Pages
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FM1608B
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum junction temperature ................................... 95 C
Supply voltage on VDD relative to VSS ........–1.0 V to + 7.0 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Input voltage .......... –1.0 V to + 7.0 V and VIN < VDD + 1.0 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............ 4 kV
Charged Device Model (AEC-Q100-011 Rev. B) .. 1.25 kV
Machine Model (AEC-Q100-003 Rev. E) ................. 300 V
Latch-up current ................................................... > 140 mA
Operating Range
Range
Industrial
Ambient Temperature (TA)
VDD
–40 C to +85 C
4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VDD
IDD
ISB1
ISB2
ILI
ILO
VIH
VIL
VOH1
VOH2
VOL1
VOL2
Description
Test Conditions
Min
Typ [1] Max
Unit
Power supply voltage
4.5
5.0
5.5
V
VDD supply current
Standby current (TTL)
Standby current (CMOS)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
VDD = 5.5 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
VDD = 5.5 V, CE at VIH, All other pins are static
and at TTL levels (0.2 V or VDD – 0.2 V)
VDD = 5.5 V, CE at VIH, All other pins are static
and at CMOS levels (0.2 V or VDD – 0.2 V)
VIN between VDD and VSS
VOUT between VDD and VSS
2.0
– 0.3
15
mA
1.8
mA
25
50
µA
+1
µA
+1
µA
– VDD + 0.3 V
0.8
V
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
IOH = –2.0 mA
IOH = –100 µA
IOL = 4.2 mA
IOL = 150 µA
2.4
VDD – 0.2 –
V
V
0.4
V
0.2
V
Data Retention and Endurance
Parameter
Description
TDR
Data retention
NVC
Endurance
Test condition
At +85 C
At +75 C
At +65 C
Over operating temperature
Note
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
Document Number: 001-86211 Rev. *C
Min
10
38
151
1014
Max
Unit
Years
Cycles
Page 7 of 18

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