TQ5631 Ver la hoja de datos (PDF) - TriQuint Semiconductor
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TQ5631 Datasheet PDF : 14 Pages
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TQ5631
Data Sheet
tuning inductor which provides a potential ground loop path.
One could use the evaluation board as an example of proper
layout techniques.
It is important to position the LO tuning and the GIC components
as close to the chip as possible. If the components are placed
too far from the chip the PC board traces can act as quarter
wave resonators in the 5-10GHz region. If both the GIC and the
LO paths to ground resonate at the same frequency, oscillation
can result, especially if Q is very high.
It is most important that the ground on the GIC bypass cap, the
LO tuning bypass capacitor, and the IF shunt cap return back to
chip pins 1 and 2 with minimal inductance. This requires that
ground returns utilize vias at a number of locations.
Solid grounding of the LO tuning inductor and bypass capacitor
will result in higher tuning circuit Q. The higher the Q, the
greater the LO drive to the mixer will be and IIP3 performance
will also improve with higher Q.
LO Buffer Tuning
Because of the broadband input match of the L0 buffer amplifier,
thermal and induced noise at other frequencies can be amplified
and injected directly into the L0 port of the mixer. Noise at the IF
frequency, and at L0 +/- IF will be downconverted and emerge
at the IF port, degrading the downconverter noise figure.
For maximum flexibility the high band TQ5631 device has the
output node of the L0 buffer amplifier brought out to Pin 6. By
connecting an external inductor between the pin and Vdd, LO
tuning can be varied. This inductor is selected to resonate with
internal capacitance at the L0 frequency in order to roll off out-
of-band gain and improve noise performance. This approach
allows selectivity in the L0 buffer amplifier along with the ability
to use the TQ5631 with multiple IF’s.
Calculation of Nominal L Value
The proper inductor value must be determined during the design
phase. The internal capacitance at Pin 6 is approximately 1.6
pF. Stray capacitance on the board surrounding Pin 6 will add to
the internal capacitance, so the nominal value of inductance can
be calculated, but must be confirmed with measurements on a
board approximating the final layout (see Figure 2).
Additionally, there is already approximately 1.3nH of inductance
from the die out to the pin which much be subtracted off of the
needed inductance value.
1 GND
GND
2
IF
3
GIC
4
RF
IN
8
VDD
7
COAXIAL
PROBE
VDD
LO TUNE
6
LO/C3
5
IF GAIN
SELECT, C3
LO IN
PORT 1
MEASURE S21
NETWORK
ANALYZER
Figure 2 LO Tuning Setup
The inductor is selected that would resonate with the total
capacitance at the L0 frequency using the following equation:
1
L = ---------------- - 1.3nH where C=1.6pF
C (2*pi*F)2
To fine tune the LO, two methods have been proven to work
well:
a) Select the inductance (next standard value) which is higher
than the calculated value derived from the equation above.
Then select a bypass capacitor that forms a resonant
circuit with the inductor. The bypass capacitor can be used
to fine tune the resonant frequency.
b) The second method relies on moving the bypass capacitor
relative to the tuning inductor. This varies the amount of
inductance in the circuit and provides a means to fine tune
the LO. This method is utilized on the test boards.
8
For additional information and latest specifications, see our website: www.triquint.com
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