SM5903BF(1999) Ver la hoja de datos (PDF) - Nippon Precision Circuits
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SM5903BF
(Rev.:1999)
(Rev.:1999)
Nippon Precision Circuits
SM5903BF Datasheet PDF : 31 Pages
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SM5903BF
Microcontroller interface (YMCLK, YMDATA, YMLD, ZSENSE pins)
Parameter
Symbol
YMCLK LOW-level pulsewidth
YMCLK HIGH-level pulsewidth
YMDATA setup time
YMDATA hold time
YMLD LOW-level pulsewidth
YMLD setup time
YMLD hold time
Rise time
Fall time
ZSENSE output delay
Note. tCY is the system clock cycle time (59ns typ).
tMCWL
tMCWH
tMDS
tMDH
tMLWL
tMLS
tMLH
tr
tf
tPZS
Rating
Unit
Min
30 + 2tCY
30 + 2tCY
30 + tCY
30 + tCY
30 + 2tCY
30 + tCY
30 + tCY
Typ
Max
ns
ns
ns
ns
ns
ns
ns
100
ns
100
ns
100 + 3tCY ns
YMDATA
YMCLK
YMLD
ZSENSE
t MDS
t MDH
t MCWL
t MLS
t MCWH
t MLH
t MLWL
t PZS
0.5VDD
0.5VDD
0.5VDD
0.5VDD
YMCLK
YMDATA
YMLD
tf
0.7 VDD
0.3 VDD
tr
0.7 VDD
0.3 VDD
0.5VDD
Reset input (NRESET pin)
Parameter
Symbol
Rating
Unit
First HIGH-level after supply voltage rising edge
NRESET pulsewidth
Min
Typ
Max
tHNRST
0
tCY (Note)
tNRST
64
tCY (Note)
Note. tCY is the system clock (CLK) input (384fs) cycle time.
tCY = 59 ns, tNRST (min) = 3.8 µs when fs = 44.1 kHz
VDD1,VDD2
NRESET
t HNRST
t NRST
NIPPON PRECISION CIRCUITS-7
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